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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by MW2PEPF00014678.mail.protection.outlook.com (10.167.249.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Wed, 14 Oct 2026 05:36:41 +0000 Received: from BLR-L1-SARUNKOD.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Wed, 14 Oct 2026 00:36:31 -0500 From: Sairaj Kodilkar To: =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , "Michael S. Tsirkin" , Alejandro Jimenez , Ani Sinha , "Igor Mammedov" , Jason Wang , "Marcelo Tosatti" , Paolo Bonzini , "Richard Henderson" , Sairaj Kodilkar , Yi Liu , , CC: , Subject: [PATCH 5/8] i386/kvm: Use x86_iommu_device_get() for per-device IOMMU lookup Date: Wed, 14 Oct 2026 11:04:30 +0530 Message-ID: <20261014053433.24564-6-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014053433.24564-1-sarunkod@amd.com> References: <20261014053433.24564-1-sarunkod@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW2PEPF00014678:EE_|CY8PR12MB7121:EE_ X-MS-Office365-Filtering-Correlation-Id: dda4cd70-cad7-4992-326d-08df29b52042 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|23010399003|36860700016|82310400026|921020|56012099006|11063799006|261009220027099003|261009223027099003|261009223327099003|261009221227099003|261009221727099003|10067099003|22082099003|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: oAuFSwr3738t68Vbn+7z5j4FE0v7QFecVdlmH60iqPHk39Xa2zwLzsFeN6RdhtjPynbkp7LZqXHx0eY0vAs5JSt/tHyUqAHUOKHLpXI+ZGTq+/vZ9Tmhu+eHIDGGb4od262W9x83YZMeWldCtnFPwn4l/ccE/W7/tUF+hXMX1D9ARR0AiK+D39dfcujgV/4hrO3/Uupp9P/akQNP4Fkv8kEyemyAD7yU50FlThaim/QKk5rJHDcisbwnN/lAy5heeIrGj++VJfR3CfGsesHH7wDdIudJEpdOulmkmlRV9VjKgBmf4eGEPECmuSdwzL1AKamgTDxw0jR95wstWl85Tiywy036+AvFNMJCOsQ73ZAU/ccGouGeX1ygDbsjD7Ge3XstP7wZX5HChh6LxCneBFTSRj/oW5vlTSI2EB4CX3fJsvCWoD1U4m2khEgk+PcTmWN+eJSDch3KUP+bM6bJf8EkhE4/EcKQeBaUMNrtdYunylNpFB7VreGOBa4/gNjoy2JHSavncVgq66w5T2fN1fcm3GmDV0VkXYWzIzxKH3rfrm8YJ0ZAxKIsTQdXH45KrjtJKHPJsddPR4zVRFiZe5qgEql52JUlRMqt1FyNTeZJU7OM4nDDcF9sZ281R+LuyX7xB0fY1diWXzNQoyyBFtKTZ95HypF8rQLaCsIsh8RXmM5NdANgePJTEtIITlfpNhAMfWQu/HAIG6TVLncYVsyOcpNYTypEGoVUUWCnqxCoCKCzIU6Wu6mbCEcr60n1 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(23010399003)(36860700016)(82310400026)(921020)(56012099006)(11063799006)(261009220027099003)(261009223027099003)(261009223327099003)(261009221227099003)(261009221727099003)(10067099003)(22082099003)(18002099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yD4t1i60Nu0fd8uXfpsW8ag9RC+ppqZIjORdwBc5MpqjaMZ+rJ/XfjT20CK/iwkUXf1bWRn5W8LWbJph+5xYrYTjnCbAFxJc6BAUDkWa99jp3QtlWEItHQSMrt353Cd2r1++GWnBFB4BYKyqNS+zB2ouQw1qaHywExBtNXHEQGJP6Mbqy4H8UqdSszhqP4ZXVWpiD1R7ovPQSNccY+d3r31XVCbChq7Ls/HQXtEpNxcoJucIhWagceFe4XlwMZUxOtntcg86HEXr+0ZooW/PIRXV3LEb2mH5ibXiBAGIq9A80W8+gu3pZwAxxC35/67lByK7PfEli9ehesaqKu5PKqreRRc7XoELNtYLAG9H4rOHk//msyt+Hi4hBa+O4p3CALVBZK5sg6sPDr18LRCvKbmxtFfOHVpxscrBb9a7DH7/Uz9kk8l0augad3W/ZYRv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2026 05:36:41.6237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dda4cd70-cad7-4992-326d-08df29b52042 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW2PEPF00014678.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7121 Currently, kvm_arch_fixup_msi_route() unconditionally uses the default system IOMMU for interrupt remapping when IOMMU is present. This approach fails when an IOMMU is attached to a non-system bus and serves only a subset of devices, because the kernel does not program IRT (Interrupt Remapping Table) entries for devices outside the IOMMU's scope. This patch changes the behavior to perform per-device IOMMU lookup: - For PCI devices: Use pci_device_get_x86_iommu() to find the specific IOMMU serving that device, if any - For non-PCI devices (IOAPIC): Fall back to the default IOMMU only if interrupt remapping is enabled (ioapic_as != address_space_memory) This ensures MSI route translation occurs only for devices actually managed by an IOMMU, enabling proper interrupt remapping in configurations where IOMMUs are attached to arbitrary buses. NOTE: This patch assumes that only non-PCI device calling is IOAPIC and checks ioapic_as to determine interrupt remapping. Signed-off-by: Sairaj Kodilkar --- hw/intc/ioapic.c | 3 ++- target/i386/kvm/kvm.c | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 1b3f1e824ac4..f1b881ee6118 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -438,8 +438,9 @@ static void ioapic_machine_done_notify(Notifier *notifier, void *data) #ifdef ACCEL_GSI_IRQFD_POSSIBLE IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, machine_done); + X86MachineState *x86ms = X86_MACHINE(qdev_get_machine()); - if (accel_irqchip_is_split()) { + if (accel_irqchip_is_split() && x86ms->ioapic_as != &address_space_memory) { X86IOMMUState *iommu = x86_iommu_get_default(); if (iommu) { /* Register this IOAPIC with IOMMU IEC notifier, so that diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 644c45fb0a02..ffe977ceb418 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -6746,7 +6746,15 @@ uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address) int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, uint64_t address, uint32_t data, PCIDevice *dev) { - X86IOMMUState *iommu = x86_iommu_get_default(); + X86IOMMUState *iommu = NULL; + MachineState *ms = MACHINE(qdev_get_machine()); + X86MachineState *x86ms = X86_MACHINE(ms); + + if (dev) { + iommu = x86_iommu_device_get(dev); + } else if (x86ms->ioapic_as != &address_space_memory) { + iommu = x86_iommu_get_default(); + } if (iommu) { X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu); @@ -6848,6 +6856,7 @@ int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, { static bool notify_list_inited = false; MSIRouteEntry *entry; + X86IOMMUState *iommu = NULL; if (!dev) { /* These are (possibly) IOAPIC routes only used for split @@ -6867,13 +6876,13 @@ int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, if (!notify_list_inited) { /* For the first time we do add route, add ourselves into * IOMMU's IEC notify list if needed. */ - X86IOMMUState *iommu = x86_iommu_get_default(); + iommu = x86_iommu_device_get(dev); if (iommu) { x86_iommu_iec_register_notifier(iommu, kvm_update_msi_routes_all, NULL); + notify_list_inited = true; } - notify_list_inited = true; } return 0; } -- 2.34.1