From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE964D4886; Thu, 15 Oct 2026 10:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792058748; cv=none; b=n3dBBlcifwSfv3J18TsKVyM72sSyenKRqrB/hyLh4YDgoW5XaNeGHEj5XPYrnlQ1tF8hqOrNeyQDVqEQ1q5k/8k9tqyNIXU0Xh8uiwf3a6cW4ZIbRpaOieLBMNg0ztD/PdrKv+9a37r9NrfQztBUu2s+bjj8DWEDSOiSHJXRm3Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792058748; c=relaxed/simple; bh=PHkaRGI9OM3TJMImu94vKZT9MncRHeIKrwCqvdXOSLY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BEKI+0XrQ52tlEZrb4r6g8jhHzHHoxbJbKJuYreMd9EWE1L6C3cVLHkrfj9a5499dBMG6S2cvp3a65MGT0CB/3C8NMssHUcjc598RfVyiSS0A3O16jJvww8Oqx3GhJrKD7zKihra6K5fvS1LzTfZEnxqIDzVBLO4JneKGoAJqtU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gJ0MaTAQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gJ0MaTAQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91F541F000CC; Thu, 15 Oct 2026 10:05:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792058745; bh=ftytAGPe4YrhA1Qp2eSKEYuT3rIyTX09UwrCpO23iSw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gJ0MaTAQt3wPeQOOmR8P8AB084F0RwNTZIjm6awP5V9+qu61z6BCFN3xX/MyUYE2C YqqXULC4zArQRMKhVggM1pnyJHoYVcudr3T1X5NEFqg4jVMr4WUBToE1UsKKocEws5 Ck2B0/hxj6w8yszoLhEI9zlP1JPca6K/bAfloUF7BsuLJkpZnVr6AtCUWSHaPNyNRP UA5k+/+dAh+4RvaHwMjbNe6BFkPH5/5HmtPWThpCGAAkDoCQ64E4j4uuGE2vcB04Ea G2abFJW+warvzmahA+foKK+dYRaB/i5bJRLOOOlDn5jU0xGayXXvjE6jCtwL5GkocO e/R1snzAJnASw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xHILH-00000003EfK-3mSN; Thu, 15 Oct 2026 10:05:43 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Steffen Eiden , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , stable@vger.kernel.org Subject: [PATCH 6/7] KVM: arm64: vgic: Stop the target vcpu when disabling LPIs Date: Thu, 15 Oct 2026 11:05:38 +0100 Message-ID: <20261015100539.1011760-7-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261015100539.1011760-1-maz@kernel.org> References: <20261015100539.1011760-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, seiden@linux.ibm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, fuad.tabba@linux.dev, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Disabling LPIs is pretty nasty, as it directly messes with the AP list of the affected CPU, which could be running... This has the potential to lead to really bad behaviours, and we should not be doing that. Take example on the way the Active state is handled and simply pause the the vcpu so that we are sure it is in a quiescent state, and the state be safely manipulated. Nobody has any expectation of performance for this anyway. Fixes: 96085b949672d ("KVM: arm/arm64: vgic-v3: Retire pending interrupts on disabling LPIs") Co-developed-by: Oliver Upton Signed-off-by: Oliver Upton Signed-off-by: Marc Zyngier Cc: stable@vger.kernel.org --- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index 5913a20d83019..f5bd29fbe3a90 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -303,9 +303,19 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, if (ctlr != GICR_CTLR_ENABLE_LPIS) return; + /* + * Yes, disabling LPIs is painful, since it can be done from + * a *remote* vcpu! So let's not take any chance, and make + * sure that the target vCPU has written their LRs back to the + * irq structures, and release any reference they would have. + * + * If it hurts, don't do it. + */ + kvm_pause_vcpu(vcpu); vgic_flush_pending_lpis(vcpu); vgic_its_invalidate_all_caches(vcpu->kvm); atomic_set_release(&vgic_cpu->ctlr, 0); + kvm_resume_vcpu(vcpu); } else { ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0, GICR_CTLR_ENABLE_LPIS); -- 2.47.3