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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91bcba3e3a0sm23953506d6.9.2026.10.16.07.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 07:25:36 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xHisJ-00000001pql-49O3; Fri, 16 Oct 2026 11:25:35 -0300 Date: Fri, 16 Oct 2026 11:25:35 -0300 From: Jason Gunthorpe To: Gong Shuai Cc: alex@ghiti.fr, andrew.jones@oss.qualcomm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, fangyu.yu@linux.alibaba.com, gsh517025@gmail.com, iommu@lists.linux.dev, joro@8bytes.org, kevin.tian@intel.com, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pbonzini@redhat.com, pjw@kernel.org, robin.murphy@arm.com, seanjc@google.com, tomasz.jeznach@linux.dev, will@kernel.org, wu.fei9@sanechips.com.cn, zhao.qingye@sanechips.com.cn Subject: Re: [RFC PATCH 0/12] iommu/riscv: Add nested translation (vIOMMU) support Message-ID: <20261016142535.GD14213@ziepe.ca> References: <20261016000004.GB14213@ziepe.ca> <20261016091610.13912-1-gong.shuai@sanechips.com.cn> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261016091610.13912-1-gong.shuai@sanechips.com.cn> On Fri, Oct 16, 2026 at 05:16:10PM +0800, Gong Shuai wrote: > Hi Jason, > > Thanks for the review again. > > > > Add nested translation support to the RISC-V IOMMU driver, so a KVM guest > > > with its own vIOMMU can own the first stage of a device context while the > > > host keeps the second stage, and add the interrupt support. This is an RFC > > > and comments on the design are welcome. > > > > The iommufd parts looked reasonable to me > > > > I feel some mild skepticism about all the MSI parts, it would be good > > to get more of the interrupt stuff actually landed before posting this > > again. > > Agreed on the MSI parts. They are a working proof to exercise the > nested flow end to end, not a finished design. The reason they are > in this series at all is that the NVMe device we use for testing > depends on MSI interrupts. Without this support, DMA succeeds but > the MSIs fault, so the driver ends up polling for completions after > timeouts. > > We will keep following the irqbypass groundwork as it evolves, and > continue this work once it has landed. It seems to me the riscv interrupt architecture is a terrible fit for Linux, so I would prefer you keep that out of a viommu series and try to address interrupt support in VFIO through the other series. viommu shouldn't change anything about how interrupts work.. Without the msi stuff I think you could get this merged without a big trouble. Jason