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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f1a197bd2sm231474285a.29.2026.10.16.07.58.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 07:58:44 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xHjON-00000001tP5-3WxW; Fri, 16 Oct 2026 11:58:43 -0300 Date: Fri, 16 Oct 2026 11:58:43 -0300 From: Jason Gunthorpe To: Baolu Lu Cc: Xu Yilun , iommu@lists.linux.dev, x86@kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Kevin Tian , Kiryl Shutsemau , Rick Edgecombe , xiaoyao.li@intel.com, Chao Gao , Binbin Wu , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/4] coco/tdx-host: Initialize trusted DMA on all capable IOMMUs Message-ID: <20261016145843.GF14213@ziepe.ca> References: <20261015010705.1973284-1-baolu.lu@linux.intel.com> <20261015010705.1973284-5-baolu.lu@linux.intel.com> <20261015173707.GV14213@ziepe.ca> <5ca5f1c4-4c3c-47f1-b79c-c1fe06b20ee4@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5ca5f1c4-4c3c-47f1-b79c-c1fe06b20ee4@linux.intel.com> On Fri, Oct 16, 2026 at 03:03:23PM +0800, Baolu Lu wrote: > On 10/16/2026 1:37 AM, Jason Gunthorpe wrote: > > On Thu, Oct 15, 2026 at 04:31:31PM +0800, Xu Yilun wrote: > > > > > An alternative could be, bringing up one IOMMU when an associated > > > device requests link encryption. Then a no-tdx-support iommu fails the > > > encryption request naturally. > > That is what ARM is planning to do. I think it is reasonable to > > trigger creation of the secure iommu when the TSM is connected to TDX. > > > > Fail connect if the iommu could not be created. > > Yes, agreed. The Intel iommu driver could use per-device interfaces, > just as ARM is planning. There are some differences, though. > > ARM's interaction with the iommu driver in viommu_init() appears to > consist of two steps: > > - arm_smmu_get_realm_params(dev, ¶ms): get and validate the > physical iommu information from the arm-smmu-v3 driver; > - cca_psmmu_get(¶ms): activate the physical smmu for Realm use. Okay, I haven't looked, not sure what is in cca_psmmu_get() yet > So the Intel iommu driver will probably end up with interfaces like: > > - dmar_tdxcs_iommu_init(struct device *dev, ...); > - dmar_tdxcs_iommu_release(struct device *dev, ...); > > These would be called from the connect and disconnect callbacks of > the TDX link ops: It seems OK It sounds like you will have a one time init of the secure iommu at the time the first PCI device wants to use the TSM? It seems like no problem. Jason