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[2a02:3100:ad43:d501:2c28:bb72:120d:420e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828cd1sm10215624f8f.22.2026.10.21.23.46.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 21 Oct 2026 23:46:39 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 0/3] KVM: arm64: Preserve level IRQ re-pending Date: Thu, 22 Oct 2026 08:46:25 +0200 Message-Id: <20261022064628.4206-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) X-Mailing-List: kvm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit A guest can set a level interrupt pending again while handling it. The GIC records Active and Pending and delivers the interrupt after deactivation. KVM instead drops the second pending state for both the GICv2 and GICv3 backends. The VGIC keeps software pending state outside the LR because commit 67b5b673ad4d stopped placing Pending and Active together for level interrupts. When the LR is folded, KVM cannot distinguish the pending state used to populate the LR from a later ISPENDR write. This series records the later write and preserves it across deactivation. The last patch adds a two-vCPU GICv3 selftest. The awkward case, and the reason for the RFC, is a write from another vCPU while the interrupt remains in an LR. KVM cannot know whether the write preceded or followed the guest ack. This series preserves the write. A pre-ack write can therefore cause one extra delivery, while a post-ack write is no longer lost. The exact alternative is to stop and synchronize the target vCPU before applying such a write, as the active-state accessors do. Is the conservative replay acceptable here, or should ISPENDR pay that synchronization cost? The issue was reproduced with Zephyr, NuttX and RT-Thread guests. On a Raspberry Pi 400 host with a GIC-400, each GICv2 guest handled the SPI once before the fix and twice afterwards. A direct GIC-400 register test also delivered the interrupt twice. With a QEMU TCG GICv3 host running KVM, the new selftest failed before the fix and passed afterwards. Existing vgic_irq and kvm-unit-tests GIC cases passed on both versions. Those runtime tests used 8623551a424d. The series applies without conflicts to kvmarm/next at dd0bc00e3e92. The modified VGIC objects pass an arm64 GCC 14 W=1 build there, and the selftest builds natively on arm64. GICv5 does not use the LR path changed here. I have not tested a mapped physical interrupt or VFIO. Karl Mehltretter (3): KVM: arm64: vgic-v2: Don't drop pending writes to active level IRQs KVM: arm64: vgic-v3: Don't drop pending writes to active level IRQs KVM: selftests: arm64: Test pending writes to active level IRQs arch/arm64/kvm/vgic/vgic-mmio.c | 9 ++ arch/arm64/kvm/vgic/vgic-v2.c | 13 ++- arch/arm64/kvm/vgic/vgic-v3.c | 13 ++- include/kvm/arm_vgic.h | 1 + tools/testing/selftests/kvm/arm64/vgic_irq.c | 101 +++++++++++++++++++ 5 files changed, 131 insertions(+), 6 deletions(-) base-commit: dd0bc00e3e9201fd49b62ff9cc07890c89003afe -- 2.39.5 (Apple Git-154)