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[24.85.96.29]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb0981c5desm111713a12.27.2026.10.29.20.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 20:29:53 -0700 (PDT) From: Mahmoud Abumandour To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mahmoud Abumandour Subject: [PATCH v2 2/2] KVM: selftests: Verify that L2's LMSW leaves L1-owned CR0 bits alone Date: Thu, 29 Oct 2026 20:29:37 -0700 Message-Id: <20261030032937.2813-3-ma.mandourr@gmail.com> X-Mailer: git-send-email 2.40.1.windows.1 In-Reply-To: <20261030032937.2813-1-ma.mandourr@gmail.com> References: <20261030032937.2813-1-ma.mandourr@gmail.com> X-Mailing-List: kvm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Verify that an LMSW in L2 that exits to L0 only leaves an L1-owned CR0.TS=0D set, and that L2 reads an L1-owned CR0.NE from the read shadow.=0D =0D Assisted-by: LLM=0D Signed-off-by: Mahmoud Abumandour =0D ---=0D .../kvm/x86/nested_exceptions_test.c | 36 +++++++++++++++++++=0D 1 file changed, 36 insertions(+)=0D =0D diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c b/too= ls/testing/selftests/kvm/x86/nested_exceptions_test.c=0D index f47432526e..e33d2e0db0 100644=0D --- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c=0D +++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c=0D @@ -109,6 +109,40 @@ static void l1_svm_code(struct svm_test_data *svm)=0D GUEST_DONE();=0D }=0D =0D +static u64 l2_cr0;=0D +=0D +static void l2_lmsw_test(void)=0D +{=0D + /* Toggle CR0.MP, which KVM intercepts and L1 doesn't. */=0D + asm volatile("lmsw %w0" : : "r" (get_cr0() ^ X86_CR0_MP));=0D + l2_cr0 =3D get_cr0();=0D + asm volatile("fnop" ::: "memory");=0D + GUEST_FAIL("L2's FNOP didn't take #NM");=0D +}=0D +=0D +/*=0D + * L1 owns CR0.TS (set) and CR0.NE, both with a read shadow of 0. L2's LM= SW=0D + * must leave both alone: FNOP takes #NM and L2 reads both as 0.=0D + */=0D +static void vmx_run_l2_lmsw(void)=0D +{=0D + u64 cr0 =3D vmread(GUEST_CR0);=0D +=0D + vmwrite(CR0_GUEST_HOST_MASK, X86_CR0_TS | X86_CR0_NE);=0D + vmwrite(CR0_READ_SHADOW, cr0 & ~(X86_CR0_TS | X86_CR0_NE));=0D + vmwrite(GUEST_CR0, cr0 | X86_CR0_TS);=0D + vmwrite(EXCEPTION_BITMAP, BIT(NM_VECTOR));=0D + vmwrite(GUEST_RIP, (u64)l2_lmsw_test);=0D + vmresume();=0D +=0D + GUEST_ASSERT_EQ(vmread(VM_EXIT_REASON), EXIT_REASON_EXCEPTION_NMI);=0D + GUEST_ASSERT_EQ(vmread(VM_EXIT_INTR_INFO) & 0xff, NM_VECTOR);=0D + GUEST_ASSERT_EQ(l2_cr0, (cr0 & ~(X86_CR0_TS | X86_CR0_NE)) ^ X86_CR0_MP);= =0D +=0D + vmwrite(CR0_GUEST_HOST_MASK, 0);=0D + vmwrite(GUEST_CR0, cr0);=0D +}=0D +=0D static void vmx_run_l2(void *l2_code, int vector, u32 error_code)=0D {=0D vmwrite(GUEST_RIP, (u64)l2_code);=0D @@ -149,6 +183,8 @@ static void l1_vmx_code(struct vmx_pages *vmx)=0D vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_DF);=0D vmx_run_l2(l2_ss_injected_df_test, DF_VECTOR, DF_ERROR_CODE);=0D =0D + vmx_run_l2_lmsw();=0D +=0D vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS);=0D vmx_run_l2(l2_ss_injected_tf_test, FAKE_TRIPLE_FAULT_VECTOR, 0);=0D GUEST_ASSERT_EQ(vmread(VM_EXIT_REASON), EXIT_REASON_TRIPLE_FAULT);=0D -- =0D 2.25.1=0D =0D