From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E37E3383339; Mon, 13 Jul 2026 07:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783926739; cv=none; b=Rgx5BWPRChReXwjFkm4o1kCwgYMKwEGIQaUy9upnkyUmZHWUL90GjIfMtq3iruxlUX2Yu4c4h+qyvUM0jk59Gn00C9+cI72aOgRUiULaSLRyPFMaCX/kDqh+qf9oz3qGFThHv7+6C153blMBU+AZ+kqDtrQ+XoXO22bCdyCeH/g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783926739; c=relaxed/simple; bh=y00wgfZkQUqELdMacPFk5NPlzw4yYP3N8JPQqTQQflU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=FxfxkWiqgYjQs2CeWlQtPa1nrn5FRw2bo25aY9GoKEzgXQABcsg2bSuz3ZEV1kWRIpWpVw+DAfzZpkEEz5K5/4hRL7SoQG6RFmee28la1Ow9Guc+3sztvTENvHNe68nZ8RHjrnD4eaiqPksOQbGxlvDyQjgPWnUtZCKlYa2vhUA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DwTQT15j; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DwTQT15j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783926738; x=1815462738; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=y00wgfZkQUqELdMacPFk5NPlzw4yYP3N8JPQqTQQflU=; b=DwTQT15j7iDki5UXSjcSUHMJ65fhnZJfLRHZTDIDvU+dYDNZRVyz9BsR 0y6KgHBSeZ7shUNCtctL5MZZiFhtjLpA1RPvfyVv7IxRPeuxT0wzGUTmz KMEbn+gzrYqe1eyaiMhsTsU6xEW9oLiQKE8Ro7VuwxprTm+WrobWuoyyU 7ZnIIUAyODfQ95Qt7s31UHtRFklC9ad0W7XQ4wnGZMop96XRWzEytH/pD bcBMeLxv3GKyCoI5DB4LGHHPRhQ0JoFxD/9yA2QcvwGfhulKJUmJ+uRGg r4poe1P1V4cXNvMWINacTCzPQtd73gbnZEf2rxgKGgmrzlNeXYTQamJTW g==; X-CSE-ConnectionGUID: rtXb2VzrQiqWpY3mwBtNKA== X-CSE-MsgGUID: qu1IlbGZT3WMrLY0nU/B8Q== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="83645618" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="83645618" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 00:12:17 -0700 X-CSE-ConnectionGUID: 0b66cS40S6W5JQsUNIBWOA== X-CSE-MsgGUID: IBEwmu2BTt2+3+C9D52cqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="254340156" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.232.65]) ([10.124.232.65]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 00:12:15 -0700 Message-ID: <212b058b-5804-4a00-a95a-67f58546fd9a@linux.intel.com> Date: Mon, 13 Jul 2026 15:11:51 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 8/8] KVM: selftests: Add PERF_METRICS and fixed counter 3 tests To: Jim Mattson Cc: Zide Chen , Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mingwei Zhang , Das Sandipan , Shukla Manali , Falcon Thomas , Xudong Hao References: <20260629231938.15129-1-zide.chen@intel.com> <20260629231938.15129-9-zide.chen@intel.com> <32a1e1d2-c437-4cd1-8455-43fa9082cb50@linux.intel.com> <5760cb18-739c-4907-b582-60933d11a72d@linux.intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 7/10/2026 11:22 PM, Jim Mattson wrote: > On Fri, Jul 10, 2026 at 1:08 AM Mi, Dapeng wrote: >> >> On 7/9/2026 8:35 PM, Jim Mattson wrote: >>> On Mon, Jun 29, 2026 at 7:36 PM Mi, Dapeng wrote: >>>> On 6/30/2026 7:19 AM, Zide Chen wrote: >>>>> Add a test case to exercise IA32_PERF_METRICS, i.e. architectural >>>>> support for Topdown (TMA) Level 1 metrics, enumerated by >>>>> IA32_PERF_CAPABILITIES[15]. >>>>> >>>>> Only check for non-zero metrics, as they are derived and depend on >>>>> the workload, CPU model, and host scheduling, making precise >>>>> expectations fragile. >>>>> >>>>> Extend the PMU selftest to cover Intel fixed counter 3 by bumping >>>>> MAX_NR_FIXED_COUNTERS to 4 and validating basic functionality. >>>>> >>>>> Signed-off-by: Zide Chen >>>>> --- >>>>> ... >>>>> +static void __guest_test_perf_metrics(void) >>>>> +{ >>>>> + int retiring, bad_spec, fe_bound, be_bound, sum; >>>>> + u64 global_ctrl, metrics; >>>>> + >>>>> + if ((guest_get_pmu_version() < 2) || /* Does guest have GLOBAL_CTRL? */ >>>>> + !this_cpu_has(X86_FEATURE_PDCM) || >>>>> + !(rdmsr(MSR_IA32_PERF_CAPABILITIES) & PERF_CAP_PERF_METRICS)) >>>>> + return; >>>>> + >>>>> + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); >>>>> + wrmsr(MSR_CORE_PERF_FIXED_CTR3, 0); >>>>> + wrmsr(MSR_PERF_METRICS, 0); >>>>> + >>>>> + /* Enable fixed ctr3 (TOPDOWN.SLOTS) and PERF_METRICS. */ >>>>> + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(3, FIXED_PMC_KERNEL)); >>>>> + global_ctrl = FIXED_PMC_GLOBAL_CTRL_ENABLE(3) | >>>>> + PERF_METRICS_GLOBAL_CTRL_ENABLE; >>>>> + >>>>> + GUEST_RUN_PAYLOAD(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl, ""); >>>>> + >>>>> + /* Check test results. */ >>>>> + metrics = rdmsr(MSR_PERF_METRICS); >>>> Could we use rdpmc instead of rdmsr here? rdpmc is a preferred way to read >>>> counter value. >>> This is in-guest code, so the unintercepted RDMSR will be much faster >>> than the emulated RDPMC. >>> >>> Should we rethink that preference, or add hardware support for >>> selective RDPMC intercepts? >> Hmm, in current most cases, rdpmc and rdmsr should share consistent >> interception configuration for PERF_METRICS except host and guest have >> different counters bitmap. > I'm assuming that Intel wants to reserve the right to cover other > resources with RDPMC in the future. Unless we have some way of > determining, through a hardware enumeration, that all readable > resources contain guest state, then we will akways have to intercept > RDPMC. rdpmc is the preferable way to read PMU counters since the better performance than rdmsr, and most of current code regardless of kernel or user-space already use rdpmc to read PMC counters. If we set the rdpmc to interception by default, then it may cause extra performance hit. Currently I didn't hear there is any plan to extend the rdpmc to support more types for Intel platforms ... > > If I'm wrong, and Intel is willing to guarantee that no new resources > will ever be added, then we can let the guest execute RDPMC natively, > when the guest owns all of the counters and PERF_METRICS. >