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[47.64.115.173]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a2cee4sm2783959f8f.67.2025.05.09.03.04.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 May 2025 03:04:21 -0700 (PDT) Message-ID: <2f526570-7ab0-479c-967c-b3f95f9f19e3@redhat.com> Date: Fri, 9 May 2025 12:04:19 +0200 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: How to mark internal properties (was: Re: [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field) To: Zhao Liu , Xiaoyao Li , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Markus Armbruster , Paolo Bonzini , "Daniel P. Berrange" Cc: qemu-devel@nongnu.org, Richard Henderson , kvm@vger.kernel.org, Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , "Michael S. Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Igor Mammedov , Fabiano Rosas , Paolo Bonzini , Liu Zhiwei , =?UTF-8?Q?Cl=C3=A9ment_Mathieu--Drif?= , qemu-arm@nongnu.org, =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , Huacai Chen , Jason Wang References: <20250508133550.81391-1-philmd@linaro.org> <20250508133550.81391-13-philmd@linaro.org> <23260c74-01ba-45bc-bf2f-b3e19c28ec8a@intel.com> From: Thomas Huth Content-Language: en-US Autocrypt: addr=thuth@redhat.com; keydata= xsFNBFH7eUwBEACzyOXKU+5Pcs6wNpKzrlJwzRl3VGZt95VCdb+FgoU9g11m7FWcOafrVRwU yYkTm9+7zBUc0sW5AuPGR/dp3pSLX/yFWsA/UB4nJsHqgDvDU7BImSeiTrnpMOTXb7Arw2a2 4CflIyFqjCpfDM4MuTmzTjXq4Uov1giGE9X6viNo1pxyEpd7PanlKNnf4PqEQp06X4IgUacW tSGj6Gcns1bCuHV8OPWLkf4hkRnu8hdL6i60Yxz4E6TqlrpxsfYwLXgEeswPHOA6Mn4Cso9O 0lewVYfFfsmokfAVMKWzOl1Sr0KGI5T9CpmRfAiSHpthhHWnECcJFwl72NTi6kUcUzG4se81 O6n9d/kTj7pzTmBdfwuOZ0YUSqcqs0W+l1NcASSYZQaDoD3/SLk+nqVeCBB4OnYOGhgmIHNW 0CwMRO/GK+20alxzk//V9GmIM2ACElbfF8+Uug3pqiHkVnKqM7W9/S1NH2qmxB6zMiJUHlTH gnVeZX0dgH27mzstcF786uPcdEqS0KJuxh2kk5IvUSL3Qn3ZgmgdxBMyCPciD/1cb7/Ahazr 3ThHQXSHXkH/aDXdfLsKVuwDzHLVSkdSnZdt5HHh75/NFHxwaTlydgfHmFFwodK8y/TjyiGZ zg2Kje38xnz8zKn9iesFBCcONXS7txENTzX0z80WKBhK+XSFJwARAQABzR5UaG9tYXMgSHV0 aCA8dGh1dGhAcmVkaGF0LmNvbT7CwXgEEwECACIFAlVgX6oCGwMGCwkIBwMCBhUIAgkKCwQW AgMBAh4BAheAAAoJEC7Z13T+cC21EbIP/ii9cvT2HHGbFRl8HqGT6+7Wkb+XLMqJBMAIGiQK QIP3xk1HPTsLfVG0ao4hy/oYkGNOP8+ubLnZen6Yq3zAFiMhQ44lvgigDYJo3Ve59gfe99KX EbtB+X95ODARkq0McR6OAsPNJ7gpEUzfkQUUJTXRDQXfG/FX303Gvk+YU0spm2tsIKPl6AmV 1CegDljzjycyfJbk418MQmMu2T82kjrkEofUO2a24ed3VGC0/Uz//XCR2ZTo+vBoBUQl41BD eFFtoCSrzo3yPFS+w5fkH9NT8ChdpSlbNS32NhYQhJtr9zjWyFRf0Zk+T/1P7ECn6gTEkp5k ofFIA4MFBc/fXbaDRtBmPB0N9pqTFApIUI4vuFPPO0JDrII9dLwZ6lO9EKiwuVlvr1wwzsgq zJTPBU3qHaUO4d/8G+gD7AL/6T4zi8Jo/GmjBsnYaTzbm94lf0CjXjsOX3seMhaE6WAZOQQG tZHAO1kAPWpaxne+wtgMKthyPLNwelLf+xzGvrIKvLX6QuLoWMnWldu22z2ICVnLQChlR9d6 WW8QFEpo/FK7omuS8KvvopFcOOdlbFMM8Y/8vBgVMSsK6fsYUhruny/PahprPbYGiNIhKqz7 UvgyZVl4pBFjTaz/SbimTk210vIlkDyy1WuS8Zsn0htv4+jQPgo9rqFE4mipJjy/iboDzsFN BFH7eUwBEAC2nzfUeeI8dv0C4qrfCPze6NkryUflEut9WwHhfXCLjtvCjnoGqFelH/PE9NF4 4VPSCdvD1SSmFVzu6T9qWdcwMSaC+e7G/z0/AhBfqTeosAF5XvKQlAb9ZPkdDr7YN0a1XDfa +NgA+JZB4ROyBZFFAwNHT+HCnyzy0v9Sh3BgJJwfpXHH2l3LfncvV8rgFv0bvdr70U+On2XH 5bApOyW1WpIG5KPJlDdzcQTyptOJ1dnEHfwnABEfzI3dNf63rlxsGouX/NFRRRNqkdClQR3K gCwciaXfZ7ir7fF0u1N2UuLsWA8Ei1JrNypk+MRxhbvdQC4tyZCZ8mVDk+QOK6pyK2f4rMf/ WmqxNTtAVmNuZIwnJdjRMMSs4W4w6N/bRvpqtykSqx7VXcgqtv6eqoDZrNuhGbekQA0sAnCJ VPArerAZGArm63o39me/bRUQeQVSxEBmg66yshF9HkcUPGVeC4B0TPwz+HFcVhheo6hoJjLq knFOPLRj+0h+ZL+D0GenyqD3CyuyeTT5dGcNU9qT74bdSr20k/CklvI7S9yoQje8BeQAHtdV cvO8XCLrpGuw9SgOS7OP5oI26a0548M4KldAY+kqX6XVphEw3/6U1KTf7WxW5zYLTtadjISB X9xsRWSU+Yqs3C7oN5TIPSoj9tXMoxZkCIHWvnqGwZ7JhwARAQABwsFfBBgBAgAJBQJR+3lM AhsMAAoJEC7Z13T+cC21hPAQAIsBL9MdGpdEpvXs9CYrBkd6tS9mbaSWj6XBDfA1AEdQkBOn ZH1Qt7HJesk+qNSnLv6+jP4VwqK5AFMrKJ6IjE7jqgzGxtcZnvSjeDGPF1h2CKZQPpTw890k fy18AvgFHkVk2Oylyexw3aOBsXg6ukN44vIFqPoc+YSU0+0QIdYJp/XFsgWxnFIMYwDpxSHS 5fdDxUjsk3UBHZx+IhFjs2siVZi5wnHIqM7eK9abr2cK2weInTBwXwqVWjsXZ4tq5+jQrwDK cvxIcwXdUTLGxc4/Z/VRH1PZSvfQxdxMGmNTGaXVNfdFZjm4fz0mz+OUi6AHC4CZpwnsliGV ODqwX8Y1zic9viSTbKS01ZNp175POyWViUk9qisPZB7ypfSIVSEULrL347qY/hm9ahhqmn17 Ng255syASv3ehvX7iwWDfzXbA0/TVaqwa1YIkec+/8miicV0zMP9siRcYQkyTqSzaTFBBmqD oiT+z+/E59qj/EKfyce3sbC9XLjXv3mHMrq1tKX4G7IJGnS989E/fg6crv6NHae9Ckm7+lSs IQu4bBP2GxiRQ+NV3iV/KU3ebMRzqIC//DCOxzQNFNJAKldPe/bKZMCxEqtVoRkuJtNdp/5a yXFZ6TfE1hGKrDBYAm4vrnZ4CXFSBDllL59cFFOJCkn4Xboj/aVxxJxF30bn In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 09/05/2025 09.32, Zhao Liu wrote: > On Fri, May 09, 2025 at 02:49:27PM +0800, Xiaoyao Li wrote: >> Date: Fri, 9 May 2025 14:49:27 +0800 >> From: Xiaoyao Li >> Subject: Re: [PATCH v4 12/27] target/i386/cpu: Remove >> CPUX86State::enable_cpuid_0xb field >> >> On 5/8/2025 9:35 PM, Philippe Mathieu-Daudé wrote: >>> The CPUX86State::enable_cpuid_0xb boolean was only disabled >>> for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got >>> removed. Being now always %true, we can remove it and simplify >>> cpu_x86_cpuid(). >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>> target/i386/cpu.h | 3 --- >>> target/i386/cpu.c | 6 ------ >>> 2 files changed, 9 deletions(-) >>> >>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h >>> index 0db70a70439..06817a31cf9 100644 >>> --- a/target/i386/cpu.h >>> +++ b/target/i386/cpu.h >>> @@ -2241,9 +2241,6 @@ struct ArchCPU { >>> */ >>> bool legacy_multi_node; >>> - /* Compatibility bits for old machine types: */ >>> - bool enable_cpuid_0xb; >>> - >>> /* Enable auto level-increase for all CPUID leaves */ >>> bool full_cpuid_auto_level; >>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >>> index 49179f35812..6fe37f71b1e 100644 >>> --- a/target/i386/cpu.c >>> +++ b/target/i386/cpu.c >>> @@ -6982,11 +6982,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, >>> break; >>> case 0xB: >>> /* Extended Topology Enumeration Leaf */ >>> - if (!cpu->enable_cpuid_0xb) { >>> - *eax = *ebx = *ecx = *edx = 0; >>> - break; >>> - } >>> - >>> *ecx = count & 0xff; >>> *edx = cpu->apic_id; >>> @@ -8828,7 +8823,6 @@ static const Property x86_cpu_properties[] = { >>> DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), >>> DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), >>> DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), >>> - DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), >> >> It's deprecating the "cpuid-0xb" property. >> >> I think we need go with the standard process to deprecate it. > > Thanks! I got your point. > > Though this property is introduced for compatibility, as its comment > said "Compatibility bits for old machine types", it is also useful for > somer users. Thanks for your clarifications, Zhao! But I think this shows again the problem that we have hit a couple of times in the past already: Properties are currently used for both, config knobs for the users and internal switches for configuration of the machine. We lack a proper way to say "this property is usable for the user" and "this property is meant for internal configuration only". I wonder whether we could maybe come up with a naming scheme to better distinguish the two sets, e.g. by using a prefix similar to the "x-" prefix for experimental properties? We could e.g. say that all properties starting with a "q-" are meant for QEMU-internal configuration only or something similar (and maybe even hide those from the default help output when running "-device xyz,help" ?)? Anybody any opinions or better ideas on this? Thomas > Fo example, in the early development stages of TDX, when there was no > full support for CPU topology, Intel had disable this property for > testing and found this bug: > > https://lore.kernel.org/qemu-devel/20250227062523.124601-3-zhao1.liu@intel.com/ > > So, I think there may be other similar use cases as well. > > And, if someone wants to emulate ancient x86 CPUs (though I can't > currently confirm from which generation of CPUs 0xb support started), he > may want to consider disable this property as well. > > The main problem here is that the "property" mechanism doesn't > distinguish between internal use/public use, and although it was originally > intended for internal QEMU use, it also leaks to the user, creating some > external use cases. > > @Philippe, thank you for cleaning up this case! I think we can keep this > property, and if you don't mind, I can modify its comment later to > indicate that it's used to adjust the topology support for the CPU. > > Thanks, > Zhao > >