From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v5 4/5] KVM: VMX: Allow direct access to MSR_IA32_SPEC_CTRL Date: Thu, 1 Feb 2018 09:09:01 -0500 Message-ID: <337b9577-50bc-412f-3cf3-7d366755aa76@redhat.com> References: <1517427467-28567-1-git-send-email-karahmed@amazon.de> <1517427467-28567-5-git-send-email-karahmed@amazon.de> <06cb88da-f355-41ed-380f-7daa8ddf6159@amazon.com> <67dca2bb-1298-c7fa-f681-018e4edc6725@redhat.com> <16d89e09-fbfc-4a08-00a6-40cfb4776018@redhat.com> <1517435981.18619.215.camel@infradead.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: KarimAllah Ahmed , KarimAllah Ahmed , kvm list , LKML , the arch/x86 maintainers , Asit Mallick , Arjan Van De Ven , Dave Hansen , Andi Kleen , Andrea Arcangeli , Linus Torvalds , Tim Chen , Thomas Gleixner , Dan Williams , Jun Nakajima , Greg KH , Andy Lutomirski , Ashok Raj To: David Woodhouse , Jim Mattson Return-path: Received: from mx1.redhat.com ([209.132.183.28]:47212 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751410AbeBAOJL (ORCPT ); Thu, 1 Feb 2018 09:09:11 -0500 In-Reply-To: <1517435981.18619.215.camel@infradead.org> Content-Language: en-US Sender: kvm-owner@vger.kernel.org List-ID: On 31/01/2018 16:59, David Woodhouse wrote: > > > On Wed, 2018-01-31 at 13:53 -0800, Jim Mattson wrote: >> On Wed, Jan 31, 2018 at 1:42 PM, Paolo Bonzini wrote: >> >>> Can we just say it sucks to be L2 too? :)  Because in the end as long as >>> no one ever writes to spec_ctrl, everybody is happy. >> >> Unfortunately, quite a few OS vendors shipped IBRS-based mitigations >> earlier this month. (Has Redhat stopped writing to IA32_SPEC_CTRL yet? >> :-) >> >> And in the long run, everyone is going to set IA32_SPEC_CTRL.IBRS=1 on >> CPUs with IA32_ARCH_CAPABILITIES.IBRS_ALL. > > > I'm actually working on IBRS_ALL at the moment. > > I was tempted to *not* let the guests turn it off. Expose SPEC_CTRL but > just make it a no-op. That would be very slow. > Or if that really doesn't fly, perhaps with IBRS_ALL we should invert > the logic. Set IBRS to 1 on vCPU reset, and only if it's set to *zero* > do we pass through the MSR and set the save_spec_ctrl_on_exit flag. ... but something like that would be a good idea. Even if IBRS to 0 on vCPU reset, only pass it through once it's set to zero. The first IBRS=1 write would not enable pass through, and would not set the save_spec_ctrl_on_exit flag. In fact it need not even be conditional on IBRS_ALL. Paolo > But let's get the code for *current* hardware done first... >