From: Paolo Bonzini <pbonzini@redhat.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: seanjc@google.com, chao.gao@intel.com, zhao1.liu@intel.com
Subject: Re: [PATCH RFC v1 02/20] KVM: x86: Refactor GPR accessors to differentiate register access types
Date: Tue, 11 Nov 2025 19:11:48 +0100 [thread overview]
Message-ID: <33eacd6f-5598-49cb-bb11-ca3a47bfb111@redhat.com> (raw)
In-Reply-To: <20251110180131.28264-3-chang.seok.bae@intel.com>
On 11/10/25 19:01, Chang S. Bae wrote:
> Refactor the GPR accessors to introduce internal helpers to distinguish
> between legacy and extended registers.
>
> x86 CPUs introduce additional GPRs, but those registers will initially
> remain unused in the kernel and will not be saved in KVM register cache
> on every VM exit. Guest states are expected to remain live in hardware
> registers.
>
> This abstraction layer centralizes the selection of access methods,
> providing a unified interface. For now, the EGPR accessors are
> placeholders to be implemented later.
>
> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
> ---
> arch/x86/include/asm/kvm_host.h | 18 ++++++++++++
> arch/x86/include/asm/kvm_vcpu_regs.h | 16 ++++++++++
> arch/x86/kvm/fpu.h | 6 ++++
> arch/x86/kvm/x86.h | 44 ++++++++++++++++++++++++++--
> 4 files changed, 82 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 48598d017d6f..940f83c121cf 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -212,6 +212,24 @@ enum {
> VCPU_SREG_GS,
> VCPU_SREG_TR,
> VCPU_SREG_LDTR,
> +#ifdef CONFIG_X86_64
> + VCPU_XREG_R16 = __VCPU_XREG_R16,
> + VCPU_XREG_R17 = __VCPU_XREG_R17,
> + VCPU_XREG_R18 = __VCPU_XREG_R18,
> + VCPU_XREG_R19 = __VCPU_XREG_R19,
> + VCPU_XREG_R20 = __VCPU_XREG_R20,
> + VCPU_XREG_R21 = __VCPU_XREG_R21,
> + VCPU_XREG_R22 = __VCPU_XREG_R22,
> + VCPU_XREG_R23 = __VCPU_XREG_R23,
> + VCPU_XREG_R24 = __VCPU_XREG_R24,
> + VCPU_XREG_R25 = __VCPU_XREG_R25,
> + VCPU_XREG_R26 = __VCPU_XREG_R26,
> + VCPU_XREG_R27 = __VCPU_XREG_R27,
> + VCPU_XREG_R28 = __VCPU_XREG_R28,
> + VCPU_XREG_R29 = __VCPU_XREG_R29,
> + VCPU_XREG_R30 = __VCPU_XREG_R30,
> + VCPU_XREG_R31 = __VCPU_XREG_R31,
> +#endif
> };
>
> enum exit_fastpath_completion {
> diff --git a/arch/x86/include/asm/kvm_vcpu_regs.h b/arch/x86/include/asm/kvm_vcpu_regs.h
> index 1af2cb59233b..dd0cc171f405 100644
> --- a/arch/x86/include/asm/kvm_vcpu_regs.h
> +++ b/arch/x86/include/asm/kvm_vcpu_regs.h
> @@ -20,6 +20,22 @@
> #define __VCPU_REGS_R13 13
> #define __VCPU_REGS_R14 14
> #define __VCPU_REGS_R15 15
> +#define __VCPU_XREG_R16 16
> +#define __VCPU_XREG_R17 17
> +#define __VCPU_XREG_R18 18
> +#define __VCPU_XREG_R19 19
> +#define __VCPU_XREG_R20 20
> +#define __VCPU_XREG_R21 21
> +#define __VCPU_XREG_R22 22
> +#define __VCPU_XREG_R23 23
> +#define __VCPU_XREG_R24 24
> +#define __VCPU_XREG_R25 25
> +#define __VCPU_XREG_R26 26
> +#define __VCPU_XREG_R27 27
> +#define __VCPU_XREG_R28 28
> +#define __VCPU_XREG_R29 29
> +#define __VCPU_XREG_R30 30
> +#define __VCPU_XREG_R31 31
> #endif
>
> #endif /* _ASM_X86_KVM_VCPU_REGS_H */
> diff --git a/arch/x86/kvm/fpu.h b/arch/x86/kvm/fpu.h
> index 3ba12888bf66..159239b3a651 100644
> --- a/arch/x86/kvm/fpu.h
> +++ b/arch/x86/kvm/fpu.h
> @@ -4,6 +4,7 @@
> #define __KVM_FPU_H_
>
> #include <asm/fpu/api.h>
> +#include <asm/kvm_vcpu_regs.h>
>
> typedef u32 __attribute__((vector_size(16))) sse128_t;
> #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; }
> @@ -137,4 +138,9 @@ static inline void kvm_write_mmx_reg(int reg, const u64 *data)
> kvm_fpu_put();
> }
>
> +#ifdef CONFIG_X86_64
> +static inline unsigned long kvm_read_egpr(int reg) { return 0; }
> +static inline void kvm_write_egpr(int reg, unsigned long data) { }
> +#endif
> +
> #endif
> diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
> index 4edadd64d3d5..74ae8f12b5a1 100644
> --- a/arch/x86/kvm/x86.h
> +++ b/arch/x86/kvm/x86.h
> @@ -400,9 +400,49 @@ static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
> return false;
> }
>
> +#ifdef CONFIG_X86_64
> +static inline unsigned long _kvm_gpr_read(struct kvm_vcpu *vcpu, int reg)
> +{
> + switch (reg) {
> + case VCPU_REGS_RAX ... VCPU_REGS_R15:
> + return kvm_register_read_raw(vcpu, reg);
> + case VCPU_XREG_R16 ... VCPU_XREG_R31:
> + return kvm_read_egpr(reg);
> + default:
> + WARN_ON_ONCE(1);
> + }
> +
> + return 0;
> +}
> +
> +static inline void _kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long val)
> +{
> + switch (reg) {
> + case VCPU_REGS_RAX ... VCPU_REGS_R15:
> + kvm_register_write_raw(vcpu, reg, val);
> + break;
> + case VCPU_XREG_R16 ... VCPU_XREG_R31:
> + kvm_write_egpr(reg, val);
> + break;
> + default:
> + WARN_ON_ONCE(1);
> + }
> +}
> +#else
> +static inline unsigned long _kvm_gpr_read(struct kvm_vcpu *vcpu, int reg)
> +{
> + return kvm_register_read_raw(vcpu, reg);
> +}
Please leave these as kvm_gpr_{read,write}_raw. It's easier to review
than the leading underscore. (It's not hard to undo if you use "git
format-patch --stdout", do a mass replace on the resulting patch file,
and then reapply the patch with "git am").
Paolo
> +static inline void _kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long val)
> +{
> + kvm_register_write_raw(vcpu, reg, val);
> +}
> +#endif
> +
> static inline unsigned long kvm_gpr_read(struct kvm_vcpu *vcpu, int reg)
> {
> - unsigned long val = kvm_register_read_raw(vcpu, reg);
> + unsigned long val = _kvm_gpr_read(vcpu, reg);
>
> return is_64_bit_mode(vcpu) ? val : (u32)val;
> }
> @@ -411,7 +451,7 @@ static inline void kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long v
> {
> if (!is_64_bit_mode(vcpu))
> val = (u32)val;
> - return kvm_register_write_raw(vcpu, reg, val);
> + _kvm_gpr_write(vcpu, reg, val);
> }
>
> static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
next prev parent reply other threads:[~2025-11-11 18:11 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 18:01 [PATCH RFC v1 00/20] KVM: x86: Support APX feature for guests Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 01/20] KVM: x86: Rename register accessors to be GPR-specific Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 02/20] KVM: x86: Refactor GPR accessors to differentiate register access types Chang S. Bae
2025-11-11 18:08 ` Paolo Bonzini
2025-11-13 23:19 ` Chang S. Bae
2025-11-11 18:11 ` Paolo Bonzini [this message]
2025-11-13 23:18 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 03/20] KVM: x86: Implement accessors for extended GPRs Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 04/20] KVM: VMX: Introduce unified instruction info structure Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 05/20] KVM: VMX: Refactor instruction information retrieval Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 06/20] KVM: VMX: Refactor GPR index retrieval from exit qualification Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 07/20] KVM: nVMX: Support the extended instruction info field Chang S. Bae
2025-11-11 17:48 ` Paolo Bonzini
2025-11-12 1:54 ` Chao Gao
2025-11-13 23:21 ` Chang S. Bae
2025-11-17 23:29 ` Paolo Bonzini
2025-11-18 1:39 ` Chao Gao
2025-11-18 10:33 ` Paolo Bonzini
2025-11-13 23:20 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 08/20] KVM: VMX: Support extended register index in exit handling Chang S. Bae
2025-11-11 17:45 ` Paolo Bonzini
2025-11-13 23:22 ` Chang S. Bae
2025-11-13 23:40 ` Paolo Bonzini
2025-11-10 18:01 ` [PATCH RFC v1 09/20] KVM: x86: Support EGPR accessing and tracking for instruction emulation Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 10/20] KVM: x86: Refactor REX prefix handling in " Chang S. Bae
2025-11-11 18:17 ` Paolo Bonzini
2025-11-13 23:23 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 11/20] KVM: x86: Refactor opcode table lookup " Chang S. Bae
2025-11-11 16:55 ` Paolo Bonzini
2025-11-13 23:24 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 12/20] KVM: x86: Support REX2-extended register index in the decoder Chang S. Bae
2025-11-11 16:53 ` Paolo Bonzini
2025-11-13 23:26 ` Chang S. Bae
2025-11-11 16:53 ` Paolo Bonzini
2025-11-10 18:01 ` [PATCH RFC v1 13/20] KVM: x86: Add REX2 opcode tables to the instruction decoder Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 14/20] KVM: x86: Emulate REX2-prefixed 64-bit absolute jump Chang S. Bae
2025-11-11 16:39 ` Paolo Bonzini
2025-11-13 23:27 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 15/20] KVM: x86: Reject EVEX-prefix instructions in the emulator Chang S. Bae
2025-11-11 16:37 ` Paolo Bonzini
2025-11-13 23:28 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 16/20] KVM: x86: Decode REX2 prefix " Chang S. Bae
2025-11-11 17:55 ` Paolo Bonzini
2025-11-13 23:30 ` Chang S. Bae
2025-11-13 23:34 ` Paolo Bonzini
2025-11-17 20:01 ` Chang S. Bae
2025-11-17 23:33 ` Paolo Bonzini
2025-11-10 18:01 ` [PATCH RFC v1 17/20] KVM: x86: Prepare APX state setting in XCR0 Chang S. Bae
2025-11-11 16:59 ` Paolo Bonzini
2025-11-13 23:32 ` Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 18/20] KVM: x86: Expose APX foundational feature bit to guests Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 19/20] KVM: x86: Expose APX sub-features " Chang S. Bae
2025-11-10 18:01 ` [PATCH RFC v1 20/20] KVM: selftests: Add APX state handling and XCR0 sanity checks Chang S. Bae
2025-11-10 18:50 ` [PATCH RFC v1 00/20] KVM: x86: Support APX feature for guests Chang S. Bae
2025-11-11 18:14 ` Paolo Bonzini
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