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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9791.48 via Frontend Transport; Mon, 20 Apr 2026 06:38:58 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 20 Apr 2026 01:38:58 -0500 Received: from [10.252.234.93] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 20 Apr 2026 01:38:54 -0500 Message-ID: <34cfe5e8-756a-435a-a73d-54bf69801161@amd.com> Date: Mon, 20 Apr 2026 12:08:48 +0530 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 7/7] KVM: SVM: Add Page modification logging support To: , , CC: , , , References: <20260407063245.2755579-1-nikunj@amd.com> <20260407063245.2755579-8-nikunj@amd.com> Content-Language: en-US From: "Nikunj A. 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Let me address them here: On 4/7/2026 12:02 PM, Nikunj A Dadhania wrote: > @@ -1206,6 +1209,16 @@ static void init_vmcb(struct kvm_vcpu *vcpu, bool init_event) > if (vcpu->kvm->arch.bus_lock_detection_enabled) > svm_set_intercept(svm, INTERCEPT_BUSLOCK); > > + if (pml) { > + /* > + * Populate the page address and index here, PML is enabled > + * when dirty logging is enabled on the memslot through > + * svm_update_cpu_dirty_logging() > + */ > + control->pml_addr = (u64)__sme_set(page_to_phys(vcpu->arch.pml_page)); > + control->pml_index = PML_HEAD_INDEX; > + } > + > If the guest receives an INIT IPI and init_vmcb() is called to reset the > vCPU, does unconditionally setting pml_index to PML_HEAD_INDEX discard any > un-flushed dirty GPAs logged by the hardware? There are two scenarios where init_vmcb() is called: 1) During vCPU creation time, where we need to set pml_index to PML_HEAD_INDEX 2) During vCPU reset, when init_event=true Before vCPU reset: vcpu_enter_guest() └─> kvm_x86_call(vcpu_run) [VMRUN] └─> [guest executes, PML accumulates dirty pages] └─> VMEXIT └─> svm_handle_exit() --> PML buffer flushed here └─> return to vcpu_run() vCPU Reset: vcpu_enter_guest() ├─> kvm_check_request(KVM_REQ_EVENT) ├─> kvm_apic_accept_events() │ └─> kvm_vcpu_reset(..., true) │ └─> init_vmcb(..., true) │ └─> control->pml_index = PML_HEAD_INDEX -- PML buffer was already flushed └─> kvm_x86_call(): Next VMRUN > Could this result in the hypervisor losing track of dirty memory during live > migration, leading to memory corruption on the destination host, since > svm_flush_pml_buffer() isn't called before resetting the index? AFAIU, no. The PML buffer is always flushed opportunistically at every VM exit. > +static void svm_flush_pml_buffer(struct kvm_vcpu *vcpu) > +{ > + struct vcpu_svm *svm = to_svm(vcpu); > + struct vmcb_control_area *control = &svm->vmcb->control; > + > + /* Do nothing if PML buffer is empty */ > + if (control->pml_index == PML_HEAD_INDEX) > + return; > + > + kvm_flush_pml_buffer(vcpu, control->pml_index); > + > + /* Reset the PML index */ > + control->pml_index = PML_HEAD_INDEX; > +} > + > Since the AMD SVM architecture aggressively caches VMCB control fields across > VMRUN instructions using VMCB clean bits, will the hardware recognize this > updated pml_index? > > If the VMCB isn't explicitly marked as dirty here, for example by calling > vmcb_mark_dirty(svm->vmcb, VMCB_NPT), could the CPU continue using its > cached index? > > That cached index would be less than 0 after a PML_FULL exit, so would the > CPU immediately trigger another PML_FULL exit on the next logged write and > cause an infinite VM-Exit loop? I got clarification from the design team: No clean bits were defined for the PML_ADDR and PML_INDEX fields, so on a VMRUN, microcode always loads them from the VMCB if the feature is enabled. Regards, Nikunj 1. https://sashiko.dev/#/patchset/20260407063245.2755579-1-nikunj%40amd.com