[PATCH v2 52/54] KVM: x86/pmu/svm: Add registers to direct access list

Mingwei Zhang
2024-05-06T05:32:05Z

From: Sandipan Das <sandipan.das@amd.com>

Add all PMU-related MSRs to the list of possible direct access MSRs.
Most of them will not be intercepted when using passthrough PMU.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
arch/x86/kvm/svm/svm.c | 16 ++++++++++++++++
arch/x86/kvm/svm/svm.h | 2 +-
2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 84dd1f560d0a..ccc08c43f7fb 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -140,6 +140,22 @@ static const struct svm_direct_access_msrs {
{ .index = X2APIC_MSR(APIC_TMICT), .always = false },
{ .index = X2APIC_MSR(APIC_TMCCT), .always = false },
{ .index = X2APIC_MSR(APIC_TDCR), .always = false },
+ { .index = MSR_F15H_PERF_CTL0, .always = false },
+ { .index = MSR_F15H_PERF_CTR0, .always = false },
+ { .index = MSR_F15H_PERF_CTL1, .always = false },
+ { .index = MSR_F15H_PERF_CTR1, .always = false },
+ { .index = MSR_F15H_PERF_CTL2, .always = false },
+ { .index = MSR_F15H_PERF_CTR2, .always = false },
+ { .index = MSR_F15H_PERF_CTL3, .always = false },
+ { .index = MSR_F15H_PERF_CTR3, .always = false },
+ { .index = MSR_F15H_PERF_CTL4, .always = false },
+ { .index = MSR_F15H_PERF_CTR4, .always = false },
+ { .index = MSR_F15H_PERF_CTL5, .always = false },
+ { .index = MSR_F15H_PERF_CTR5, .always = false },
+ { .index = MSR_AMD64_PERF_CNTR_GLOBAL_CTL, .always = false },
+ { .index = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, .always = false },
+ { .index = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, .always = false },
+ { .index = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, .always = false },
{ .index = MSR_INVALID, .always = false },
};

diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 7f1fbd874c45..beb552a9ab05 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -30,7 +30,7 @@
#define IOPM_SIZE PAGE_SIZE * 3
#define MSRPM_SIZE PAGE_SIZE * 2

-#define MAX_DIRECT_ACCESS_MSRS 47
+#define MAX_DIRECT_ACCESS_MSRS 63
#define MSRPM_OFFSETS 32
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;
--
2.45.0.rc1.225.g2a3ae87e7f-goog