From: Zhi Wang <zhiw@nvidia.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
Jason Gunthorpe <jgg@nvidia.com>,
"alison.schofield@intel.com" <alison.schofield@intel.com>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"dave@stgolabs.net" <dave@stgolabs.net>,
"ira.weiny@intel.com" <ira.weiny@intel.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"alucerop@amd.com" <alucerop@amd.com>,
Andy Currid <ACurrid@nvidia.com>, Neo Jia <cjia@nvidia.com>,
Surath Mitra <smitra@nvidia.com>,
Ankit Agrawal <ankita@nvidia.com>,
Aniket Agashe <aniketa@nvidia.com>,
Kirti Wankhede <kwankhede@nvidia.com>,
"Tarun Gupta (SW-GPU)" <targupta@nvidia.com>,
"zhiwang@kernel.org" <zhiwang@kernel.org>
Subject: Re: [RFC 02/13] cxl: introduce cxl_get_hdm_info()
Date: Sat, 19 Oct 2024 05:38:53 +0000 [thread overview]
Message-ID: <38fddcd6-ebb6-4f1e-b161-61d9b95e534e@nvidia.com> (raw)
In-Reply-To: <20241017164458.00003c1f@Huawei.com>
On 17/10/2024 18.44, Jonathan Cameron wrote:
> External email: Use caution opening links or attachments
>
>
> On Fri, 20 Sep 2024 15:34:35 -0700
> Zhi Wang <zhiw@nvidia.com> wrote:
>
>> CXL core has the information of what CXL register groups a device has.
>> When initializing the device, the CXL core probes the register groups
>> and saves the information. The probing sequence is quite complicated.
>>
>> vfio-cxl requires the HDM register information to emualte the HDM decoder
> Hi Zhi,
>
> I know these were a bit rushed out so I'll only comment once.
> Give your patch descriptions a spell check (I always forget :)
> emulate
>
Thanks for pointing it out. Will proceed. Lol. Me the same. I write a
script of sending patches that ask for confirming every item was in the
checklist now.
>> registers.
>>
>> Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM
>> register information in the CXL core. Thus, it doesn't need to implement
>> its own probing sequence.
>>
>> Signed-off-by: Zhi Wang <zhiw@nvidia.com>
>> ---
>> drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++
>> drivers/cxl/cxlpci.h | 3 +++
>> include/linux/cxl_accel_mem.h | 2 ++
>> 3 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index a663e7566c48..7b6c2b6211b3 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
>>
>> +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count,
>> + u64 *hdm_reg_offset, u64 *hdm_reg_size)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(cxlds->dev);
>> + int d = cxlds->cxl_dvsec;
>> + u16 cap;
>> + int rc;
>> +
>> + if (!cxlds->reg_map.component_map.hdm_decoder.valid) {
>> + *hdm_reg_offset = *hdm_reg_size = 0;
> Probably want to zero out the hdm_count as well?
>
>> + } else {
>> + struct cxl_component_reg_map *map =
>> + &cxlds->reg_map.component_map;
>> +
>> + *hdm_reg_offset = map->hdm_decoder.offset;
>> + *hdm_reg_size = map->hdm_decoder.size;
>> + }
>> +
>> + rc = pci_read_config_word(pdev,
>> + d + CXL_DVSEC_CAP_OFFSET, &cap);
>> + if (rc)
>> + return rc;
>> +
>> + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
>> + return 0;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL);
next prev parent reply other threads:[~2024-10-19 5:38 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 22:34 [RFC 00/13] vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough Zhi Wang
2024-09-20 22:34 ` [RFC 01/13] cxl: allow a type-2 device not to have memory device registers Zhi Wang
2024-09-23 8:01 ` Tian, Kevin
2024-09-23 15:38 ` Dave Jiang
2024-09-24 8:03 ` Zhi Wang
2024-09-20 22:34 ` [RFC 02/13] cxl: introduce cxl_get_hdm_info() Zhi Wang
2024-10-17 15:44 ` Jonathan Cameron
2024-10-19 5:38 ` Zhi Wang [this message]
2024-09-20 22:34 ` [RFC 03/13] cxl: introduce cxl_find_comp_reglock_offset() Zhi Wang
2024-09-20 22:34 ` [RFC 04/13] vfio: introduce vfio-cxl core preludes Zhi Wang
2024-10-11 18:33 ` Alex Williamson
2024-09-20 22:34 ` [RFC 05/13] vfio/cxl: expose CXL region to the usersapce via a new VFIO device region Zhi Wang
2024-10-11 19:12 ` Alex Williamson
2024-09-20 22:34 ` [RFC 06/13] vfio/pci: expose vfio_pci_rw() Zhi Wang
2024-09-20 22:34 ` [RFC 07/13] vfio/cxl: introduce vfio_cxl_core_{read, write}() Zhi Wang
2024-09-20 22:34 ` [RFC 08/13] vfio/cxl: emulate HDM decoder registers Zhi Wang
2024-09-20 22:34 ` [RFC 09/13] vfio/pci: introduce CXL device awareness Zhi Wang
2024-10-11 20:37 ` Alex Williamson
2024-09-20 22:34 ` [RFC 10/13] vfio/pci: emulate CXL DVSEC registers in the configuration space Zhi Wang
2024-10-11 21:02 ` Alex Williamson
2024-09-20 22:34 ` [RFC 11/13] vfio/cxl: introduce VFIO CXL device cap Zhi Wang
2024-10-11 21:14 ` Alex Williamson
2024-09-20 22:34 ` [RFC 12/13] vfio/cxl: VFIO variant driver for QEMU CXL accel device Zhi Wang
2024-09-20 22:34 ` [RFC 13/13] vfio/cxl: workaround: don't take resource region when cxl is enabled Zhi Wang
2024-09-23 8:00 ` [RFC 00/13] vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough Tian, Kevin
2024-09-24 8:30 ` Zhi Wang
2024-09-25 13:05 ` Jonathan Cameron
2024-09-27 7:18 ` Zhi Wang
2024-10-04 11:40 ` Jonathan Cameron
2024-10-19 5:30 ` Zhi Wang
2024-10-21 11:07 ` Alejandro Lucero Palau
2024-09-26 6:55 ` Tian, Kevin
2024-09-25 10:11 ` Alejandro Lucero Palau
2024-09-27 7:38 ` Zhi Wang
2024-09-27 7:38 ` Zhi Wang
2024-10-21 10:49 ` Zhi Wang
2024-10-21 13:10 ` Alejandro Lucero Palau
2024-10-30 11:56 ` Zhi Wang
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