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Tue, 9 Aug 2022 13:53:40 +0000 Message-ID: <3fba260d-bfca-14ea-7bdd-3e55f3d1e276@arm.com> Date: Tue, 9 Aug 2022 14:53:34 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [kvm-unit-tests RFC PATCH 19/19] arm/arm64: Rework the cache maintenance in asm_mmu_disable Content-Language: en-GB To: Alexandru Elisei , pbonzini@redhat.com, thuth@redhat.com, andrew.jones@linux.dev, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu References: <20220809091558.14379-1-alexandru.elisei@arm.com> <20220809091558.14379-20-alexandru.elisei@arm.com> From: Nikos Nikoleris In-Reply-To: <20220809091558.14379-20-alexandru.elisei@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0313.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:197::12) To PAXPR08MB7017.eurprd08.prod.outlook.com (2603:10a6:102:1df::21) MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 2c2783ff-37ea-4c5a-f0ab-08da7a0e9752 X-MS-TrafficTypeDiagnostic: AS8PR08MB8222:EE_|DBAEUR03FT051:EE_|DB7PR08MB3275:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2022 13:53:51.3272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c2783ff-37ea-4c5a-f0ab-08da7a0e9752 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT051.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3275 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Alex, On 09/08/2022 10:15, Alexandru Elisei wrote: > asm_mmu_disable is overly ambitious and provably incorrect: > > 1. It tries to clean and invalidate the data caches for the *entire* > memory, which is highly unnecessary, as it's very unlikely that a test > will write to the entire memory, and even more unlikely that a test will > modify the text section of the test image. > While it appears that we don't modify the text section, there is some loading happening before we start executing a test. Are you sure that the loader doesn't leave the memory dirty? > 2. There is no corresponding dcache invalidate command for the entire > memory in asm_mmu_enable, leaving it up to the test that disabled the > MMU to do the cache maintenance in an asymmetrical fashion: only for > re-enabling the MMU, but not for disabling it. > > 3. It's missing the DMB SY memory barrier to ensure that the dcache > maintenance is performed after the last store executed in program order > before calling asm_mmu_disable. > I am not sure why this is needed. In general, iiuc, a store to location x followed by a DC CVAC to x in program order don't need an barrier (see Arm ARM ARM DDI 0487G.b "Data cache maintenance instructions" at K11.5.1 and "Ordering and completion of data and instruction cache instructions" at D4-2656). It doesn't hurt to have it but I think it's unnecessary. Thanks, Nikos > Fix all of the issues in one go, by doing the cache maintenance only for > the stack, as that is out of the control of the C code, and add the missi= ng > memory barrier. > > The code used to test that mmu_disable works correctly is similar to the > code used to test commit 410b3bf09e76 ("arm/arm64: Perform dcache clean > + invalidate after turning MMU off"), with extra cache maintenance > added: > > +#include > +#include > +#include > int main(int argc, char **argv) > { > + int *x =3D alloc_page(); > + bool pass =3D true; > + int i; > + > + for (i =3D 0; i < 1000000; i++) { > + *x =3D 0x42; > + dcache_clean_addr_poc((unsigned long)x); > + mmu_disable(); > + if (*x !=3D 0x42) { > + pass =3D false; > + break; > + } > + *x =3D 0x50; > + /* Needed for the invalidation only. */ > + dcache_clean_inval_addr_poc((unsigned long)x); > + mmu_enable(current_thread_info()->pgtable); > + if (*x !=3D 0x50) { > + pass =3D false; > + break; > + } > + } > + report(pass, "MMU disable cache maintenance"); > > Signed-off-by: Alexandru Elisei > --- > arm/cstart.S | 11 ++++++----- > arm/cstart64.S | 11 +++++------ > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arm/cstart.S b/arm/cstart.S > index fc7c558802f1..b27de44f30a6 100644 > --- a/arm/cstart.S > +++ b/arm/cstart.S > @@ -242,11 +242,12 @@ asm_mmu_disable: > mcr p15, 0, r0, c1, c0, 0 > isb > > - ldr r0, =3D__phys_offset > - ldr r0, [r0] > - ldr r1, =3D__phys_end > - ldr r1, [r1] > - dcache_by_line_op dccimvac, sy, r0, r1, r2, r3 > + dmb sy > + mov r0, sp > + lsr r0, #THREAD_SHIFT > + lsl r0, #THREAD_SHIFT > + add r1, r0, #THREAD_SIZE > + dcache_by_line_op dccmvac, sy, r0, r1, r3, r4 > > mov pc, lr > > diff --git a/arm/cstart64.S b/arm/cstart64.S > index 1ce6b9e14d23..af4970775298 100644 > --- a/arm/cstart64.S > +++ b/arm/cstart64.S > @@ -283,12 +283,11 @@ asm_mmu_disable: > msr sctlr_el1, x0 > isb > > - /* Clean + invalidate the entire memory */ > - adrp x0, __phys_offset > - ldr x0, [x0, :lo12:__phys_offset] > - adrp x1, __phys_end > - ldr x1, [x1, :lo12:__phys_end] > - dcache_by_line_op civac, sy, x0, x1, x2, x3 > + dmb sy > + mov x9, sp > + and x9, x9, #THREAD_MASK > + add x10, x9, #THREAD_SIZE > + dcache_by_line_op cvac, sy, x9, x10, x11, x12 > > ret > IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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