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Tsirkin" , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org References: <20250620092734.1576677-1-zhao1.liu@intel.com> <20250620092734.1576677-10-zhao1.liu@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250620092734.1576677-10-zhao1.liu@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/20/2025 5:27 PM, Zhao Liu wrote: > Based on legacy_l1d_cache, legacy_l1i_cache, legacy_l2_cache and > legacy_l3_cache, build a complete legacy intel cache model, which can > clarify the purpose of these trivial legacy cache models, simplify the > initialization of cache info in X86CPUState, and make it easier to > handle compatibility later. > > Signed-off-by: Zhao Liu > --- > target/i386/cpu.c | 101 +++++++++++++++++++++++++--------------------- > 1 file changed, 54 insertions(+), 47 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 0b292aa2e07b..ec229830c532 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -643,21 +643,6 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, > * These are legacy cache values. If there is a need to change any > * of these values please use builtin_x86_defs > */ > - > -/* L1 data cache: */ > -static CPUCacheInfo legacy_l1d_cache = { > - .type = DATA_CACHE, > - .level = 1, > - .size = 32 * KiB, > - .self_init = 1, > - .line_size = 64, > - .associativity = 8, > - .sets = 64, > - .partitions = 1, > - .no_invd_sharing = true, > - .share_level = CPU_TOPOLOGY_LEVEL_CORE, > -}; > - > static CPUCacheInfo legacy_l1d_cache_amd = { > .type = DATA_CACHE, > .level = 1, > @@ -672,20 +657,6 @@ static CPUCacheInfo legacy_l1d_cache_amd = { > .share_level = CPU_TOPOLOGY_LEVEL_CORE, > }; > > -/* L1 instruction cache: */ > -static CPUCacheInfo legacy_l1i_cache = { > - .type = INSTRUCTION_CACHE, > - .level = 1, > - .size = 32 * KiB, > - .self_init = 1, > - .line_size = 64, > - .associativity = 8, > - .sets = 64, > - .partitions = 1, > - .no_invd_sharing = true, > - .share_level = CPU_TOPOLOGY_LEVEL_CORE, > -}; > - > static CPUCacheInfo legacy_l1i_cache_amd = { > .type = INSTRUCTION_CACHE, > .level = 1, > @@ -700,20 +671,6 @@ static CPUCacheInfo legacy_l1i_cache_amd = { > .share_level = CPU_TOPOLOGY_LEVEL_CORE, > }; > > -/* Level 2 unified cache: */ > -static CPUCacheInfo legacy_l2_cache = { > - .type = UNIFIED_CACHE, > - .level = 2, > - .size = 4 * MiB, > - .self_init = 1, > - .line_size = 64, > - .associativity = 16, > - .sets = 4096, > - .partitions = 1, > - .no_invd_sharing = true, > - .share_level = CPU_TOPOLOGY_LEVEL_CORE, > -}; > - > static CPUCacheInfo legacy_l2_cache_amd = { > .type = UNIFIED_CACHE, > .level = 2, > @@ -803,6 +760,59 @@ static const CPUCaches legacy_intel_cpuid2_cache_info = { > }, > }; > > +static const CPUCaches legacy_intel_cache_info = { > + .l1d_cache = &(CPUCacheInfo) { > + .type = DATA_CACHE, > + .level = 1, > + .size = 32 * KiB, > + .self_init = 1, > + .line_size = 64, > + .associativity = 8, > + .sets = 64, > + .partitions = 1, > + .no_invd_sharing = true, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l1i_cache = &(CPUCacheInfo) { > + .type = INSTRUCTION_CACHE, > + .level = 1, > + .size = 32 * KiB, > + .self_init = 1, > + .line_size = 64, > + .associativity = 8, > + .sets = 64, > + .partitions = 1, > + .no_invd_sharing = true, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l2_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 2, > + .size = 4 * MiB, > + .self_init = 1, > + .line_size = 64, > + .associativity = 16, > + .sets = 4096, > + .partitions = 1, > + .no_invd_sharing = true, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l3_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 3, > + .size = 16 * MiB, > + .line_size = 64, > + .associativity = 16, > + .sets = 16384, > + .partitions = 1, > + .lines_per_tag = 1, > + .self_init = true, > + .inclusive = true, > + .complex_indexing = true, > + .share_level = CPU_TOPOLOGY_LEVEL_DIE, > + }, > +}; > + > /* TLB definitions: */ > > #define L1_DTLB_2M_ASSOC 1 > @@ -8971,10 +8981,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > env->enable_legacy_cpuid2_cache = true; > } > > - env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; > - env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; > - env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; > - env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; > + env->cache_info_cpuid4 = legacy_intel_cache_info; > > env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; > env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; Reviewed-by: Dapeng Mi