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([2001:b07:6468:f312:9af8:e5f5:7516:fa89]) by smtp.googlemail.com with ESMTPSA id j18-20020a170906411200b0099ccee57ac2sm1465845ejk.194.2023.10.05.09.51.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Oct 2023 09:51:59 -0700 (PDT) Message-ID: <4318facf-df2d-7658-39d2-d2dce1ec77d9@redhat.com> Date: Thu, 5 Oct 2023 18:51:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Content-Language: en-US To: Jim Mattson , Dave Hansen Cc: Borislav Petkov , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Pawan Gupta , Jiaxi Chen , Kim Phillips , Sean Christopherson , "H. Peter Anvin" , x86@kernel.org, Dave Hansen , Ingo Molnar , Thomas Gleixner References: <20231004002038.907778-1-jmattson@google.com> <01009a2a-929e-ce16-6f44-1d314e6bcba5@intel.com> <20231004075836.GBZR0bLC/Y09sSSYWw@fat_crate.local> From: Paolo Bonzini Subject: Re: [PATCH] x86: KVM: Add feature flag for AMD's FsGsKernelGsBaseNonSerializing In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 10/5/23 18:41, Jim Mattson wrote: >> I hope I'm not throwing stones from a glass house here... >> >> But I'm struggling to think of cases where Intel has read-only >> "defeature bits" like this one. There are certainly things like >> MSR_IA32_MISC_ENABLE_FAST_STRING that can be toggled, but read-only >> indicators of a departure from established architecture seems ... >> suboptimal. >> >> It's arguable that TDX changed a bunch of architecture like causing >> exceptions on CPUID and MSRs that never caused exceptions before and >> _that_ constitutes a defeature. But that's the least of the problems >> for a TDX VM. 😄 >> >> (Seriously, I'm not trying to shame Intel's x86 fellow travelers here, >> just trying to make sure I'm not missing something). > Intel's defeature bits that I know of are: > > CPUID.(EAX=7,ECX=0):EBX[bit 13] (Haswell) - "Deprecates FPU CS and FPU > DS values if 1." > CPUID.(EAX=7,ECX=0):EBX[bit 6] (Skylake) - "FDP_EXCPTN_ONLY. x87 FPU > Data Pointer updated only on x87 exceptions if 1." And for AMD, to get the full landscape: - CPUID(EAX=8000_0021h).EAX[0], "Processor ignores nested data breakpoints" - CPUID(EAX=8000_0021h).EAX[9], "SMM_CTL MSR is not present" (the MSR used to be always present if SVM is available) AMD had a few processors without X86_BUG_NULL_SEG that do not expose X86_FEATURE_NULL_SEL_CLR_BASE, but that's conservative so not a big deal. Paolo