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X-CSE-ConnectionGUID: mDenUyvsRU66yCdCGqBLdQ== X-CSE-MsgGUID: QqnVvuNoT4OG9HK+Lsa43A== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="66990196" X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="66990196" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 21:59:17 -0700 X-CSE-ConnectionGUID: TfAIEZKWQTmNYaUJ14lLwQ== X-CSE-MsgGUID: MxwqVamxTQWZ9eQnZIK+NA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="236677716" Received: from unknown (HELO [10.238.3.169]) ([10.238.3.169]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 21:59:14 -0700 Message-ID: <44d5687e-dcd4-491d-b5f6-0e9bf7393563@linux.intel.com> Date: Tue, 12 May 2026 12:59:11 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/9] perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM To: Sean Christopherson , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Jim Mattson , Mingwei Zhang , Stephane Eranian References: <20260508231353.406465-1-seanjc@google.com> <20260508231353.406465-8-seanjc@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260508231353.406465-8-seanjc@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/9/2026 7:13 AM, Sean Christopherson wrote: > Now that perf operates on a KVM-provided snapshot of PMU state, handled > cross-mapped PEBS counters entirely in KVM by clearing unusable counters > from the to-be-enabled mask instead of foisting the work on perf. > > No functional change intended. > > Signed-off-by: Sean Christopherson > --- > arch/x86/events/intel/core.c | 8 -------- > arch/x86/include/asm/perf_event.h | 1 - > arch/x86/kvm/vmx/vmx.c | 10 ++++++++-- > 3 files changed, 8 insertions(+), 11 deletions(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index e9acfc3f3a82..8f6be0cc4c4b 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -5053,14 +5053,6 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, > ~cpuc->intel_ctrl_exclude_guest_mask & > cpuc->intel_ctrl_exclude_host_mask; > > - /* > - * Disable counters where the guest PMC is different than the host PMC > - * being used on behalf of the guest, as the PEBS record includes > - * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the > - * wrong counter(s). > - */ > - guest_pebs_mask &= ~guest_pebs->cross_mapped_mask; > - > /* > * FIXME: Allow guest and host usage of PEBS events to co-exist instead > * of disabling guest PEBS entirely if the host is using PEBS. > diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h > index bc7e48f6f4a8..19f874a79ab0 100644 > --- a/arch/x86/include/asm/perf_event.h > +++ b/arch/x86/include/asm/perf_event.h > @@ -790,7 +790,6 @@ struct x86_guest_pebs { > u64 enable; > u64 ds_area; > u64 data_cfg; > - u64 cross_mapped_mask; > }; > #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) > extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 9f0a028cf10b..fbe3ce5f5a51 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -7319,8 +7319,14 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) > .data_cfg = pmu->pebs_data_cfg, > }; > > - if (pmu->pebs_enable & pmu->global_ctrl) > - guest_pebs.cross_mapped_mask = intel_pmu_get_cross_mapped_mask(pmu); > + /* > + * Disable counters where the guest PMC is different than the host PMC > + * being used on behalf of the guest, as the PEBS record includes > + * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the > + * wrong counter(s). > + */ > + if (guest_pebs.enable & pmu->global_ctrl) > + guest_pebs.enable &= ~intel_pmu_get_cross_mapped_mask(pmu); > > /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ > msrs = perf_guest_get_msrs(&nr_msrs, &guest_pebs); LGTM. Reviewed-by: Dapeng Mi