[PATCH] KVM: fix calculation of initial value of rdx register

[PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

On bootup, the rdx register contains information about the processor.  The
function which calculates this value has the bugs:

 - missing 'cpuid' to get the value from the processor
 - missing register clobber caused a miscompilation in some circumstances
 - we shouldn't return a value that depends on the current processor in 
   case we migrate

In any case nobody looks at the value, so just return a generic P6
identifier.

Thanks to Christian Hesse <mail-8oMOrB1mGocUSW6y5lq3GQ@public.gmane.org> for debugging help.

Signed-off-by: Avi Kivity <avi-atKUWr5tajBWk0Htik3J/w@public.gmane.org>

Index: linux-2.6/drivers/kvm/kvm_main.c
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm_main.c
+++ linux-2.6/drivers/kvm/kvm_main.c
@@ -1052,12 +1052,7 @@ static void set_cr8(struct kvm_vcpu *vcp
 
 static u32 get_rdx_init_val(void)
 {
-	u32 val;
-
-	asm ("movl $1, %%eax \n\t"
-	     "movl %%eax, %0 \n\t" : "=g"(val) );
-	return val;
-
+	return 0x600; /* P6 family */
 }
 
 static void fx_init(struct kvm_vcpu *vcpu)

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

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On Monday 06 November 2006 14:15, you wrote:
> On bootup, the rdx register contains information about the processor.  The
> function which calculates this value has the bugs:
>
>  - missing 'cpuid' to get the value from the processor
>  - missing register clobber caused a miscompilation in some circumstances
>  - we shouldn't return a value that depends on the current processor in
>    case we migrate
>
> In any case nobody looks at the value, so just return a generic P6
> identifier.

I'm sorry, but this does not change the situation for me... My system still 
freezes with the same messages.

Awaiting more patches. :)
-- 
Regards,
Chris

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
> On Monday 06 November 2006 14:15, you wrote:
>   
>> On bootup, the rdx register contains information about the processor.  The
>> function which calculates this value has the bugs:
>>
>>  - missing 'cpuid' to get the value from the processor
>>  - missing register clobber caused a miscompilation in some circumstances
>>  - we shouldn't return a value that depends on the current processor in
>>    case we migrate
>>
>> In any case nobody looks at the value, so just return a generic P6
>> identifier.
>>     
>
> I'm sorry, but this does not change the situation for me... My system still 
> freezes with the same messages.
>
> Awaiting more patches. :)
>   

Please revert all external patches (except kvm :) and try again.  I 
don't think it matters, but let's make sure.

Then, please apply the attached patch.  You will need serial console or 
netconsole, and to

   echo 9 > /proc/sysrq-trigger

before launching the VM.

BTW, what OS are you trying to run in the guest?

-- 
error compiling committee.c: too many arguments to function


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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1: Type: text/plain, Size: 1267 bytes --]

On Tuesday 07 November 2006 09:14, Avi Kivity wrote:
> Hesse, Christian wrote:
> > On Monday 06 November 2006 14:15, you wrote:
> >> On bootup, the rdx register contains information about the processor. 
> >> The function which calculates this value has the bugs:
> >>
> >>  - missing 'cpuid' to get the value from the processor
> >>  - missing register clobber caused a miscompilation in some
> >> circumstances - we shouldn't return a value that depends on the current
> >> processor in case we migrate
> >>
> >> In any case nobody looks at the value, so just return a generic P6
> >> identifier.
> >
> > I'm sorry, but this does not change the situation for me... My system
> > still freezes with the same messages.
> >
> > Awaiting more patches. :)
>
> Please revert all external patches (except kvm :) and try again.  I
> don't think it matters, but let's make sure.

You are right, it does not matter.

> Then, please apply the attached patch.  You will need serial console or
> netconsole, and to
>
>    echo 9 > /proc/sysrq-trigger
>
> before launching the VM.

There is no patch attached to this mail...

> BTW, what OS are you trying to run in the guest?

I try to boot a Windows XP SP2 install CD.
-- 
Regards,
Chris

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 617 bytes --]

Hesse, Christian wrote:
>   
>> Then, please apply the attached patch.  You will need serial console or
>> netconsole, and to
>>
>>    echo 9 > /proc/sysrq-trigger
>>
>> before launching the VM.
>>     
>
> There is no patch attached to this mail...
>
>   

Sorry, attaching now.

>> BTW, what OS are you trying to run in the guest?
>>     
>
> I try to boot a Windows XP SP2 install CD.
>   

Ok.  kvm isn't really able to complete the install (Windows will 
bluescreen) but it shouldn't lock up either.


(you can install with qemu and run with kvm

-- 
error compiling committee.c: too many arguments to function


[-- Attachment #2: kvm-debug.patch --]
[-- Type: text/x-patch, Size: 31694 bytes --]

Index: linux-2.6/drivers/kvm/debug.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.c
@@ -0,0 +1,1052 @@
+/*
+ * Kernel-based Virtual Machine driver for Linux
+ *
+ * This module enables machines with Intel VT-x extensions to run virtual
+ * machines without emulation or binary translation.
+ *
+ * Debug support
+ *
+ * Copyright (C) 2006 Qumranet, Inc.
+ *
+ * Authors:
+ *   Yaniv Kamay  <yaniv-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *   Avi Kivity   <avi-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *
+ */
+
+#include <linux/highmem.h>
+
+#include "kvm.h"
+#include "debug.h"
+
+#ifdef KVM_DEBUG
+
+static const char *vmx_msr_name[] = {
+	"MSR_EFER", "MSR_STAR", "MSR_CSTAR",
+	"MSR_KERNEL_GS_BASE", "MSR_SYSCALL_MASK", "MSR_LSTAR"
+};
+
+#define NR_VMX_MSR (sizeof(vmx_msr_name) / sizeof(char*))
+
+void show_msrs(struct kvm_vcpu *vcpu)
+{
+	int i;
+
+	for (i = 0; i < NR_VMX_MSR; ++i) {
+		vcpu_printf(vcpu, "%s: %s=0x%llx\n",
+		       __FUNCTION__,
+		       vmx_msr_name[i],
+		       vcpu->guest_msrs[i].data);
+	}
+}
+
+void show_code(struct kvm_vcpu *vcpu)
+{
+	gva_t rip = vmcs_readl(GUEST_RIP);
+	u8 code[50];
+	char buf[30 + 3 * sizeof code];
+	int i;
+
+	if (!is_long_mode())
+		rip += vmcs_readl(GUEST_CS_BASE);
+
+	kvm_read_guest(vcpu, rip, sizeof code, code);
+	for (i = 0; i < sizeof code; ++i)
+		sprintf(buf + i * 3, " %02x", code[i]);
+	vcpu_printf(vcpu, "code: %lx%s\n", rip, buf);
+}
+
+struct gate_struct {
+	u16 offset_low;
+	u16 segment;
+	unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
+	u16 offset_middle;
+	u32 offset_high;
+	u32 zero1;
+} __attribute__((packed));
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq)
+{
+	unsigned long idt_base = vmcs_readl(GUEST_IDTR_BASE);
+	unsigned long idt_limit = vmcs_readl(GUEST_IDTR_LIMIT);
+	struct gate_struct gate;
+
+	if (!is_long_mode())
+		vcpu_printf(vcpu, "%s: not in long mode\n", __FUNCTION__);
+
+	if (!is_long_mode() || idt_limit < irq * sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+
+	if (kvm_read_guest(vcpu, idt_base + irq * sizeof(gate), sizeof(gate), &gate) != sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+	vcpu_printf(vcpu, "%s: 0x%x handler 0x%llx\n",
+		   __FUNCTION__,
+		   irq,
+		   ((u64)gate.offset_high << 32) |
+		   ((u64)gate.offset_middle << 16) |
+		   gate.offset_low);
+}
+
+void show_page(struct kvm_vcpu *vcpu,
+			     gva_t addr)
+{
+	u64 *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	if (!buf)
+		return;
+
+	addr &= PAGE_MASK;
+	if (kvm_read_guest(vcpu, addr, PAGE_SIZE, buf)) {
+		int i;
+		for (i = 0; i <  PAGE_SIZE / sizeof(u64) ; i++) {
+			u8 *ptr = (u8*)&buf[i];
+			int j;
+			vcpu_printf(vcpu, " 0x%16.16lx:",
+				   addr + i * sizeof(u64));
+			for (j = 0; j < sizeof(u64) ; j++)
+				vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+			vcpu_printf(vcpu, "\n");
+		}
+	}
+	kfree(buf);
+}
+
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr)
+{
+	u64 buf;
+
+	if (kvm_read_guest(vcpu, addr, sizeof(u64), &buf) == sizeof(u64)) {
+		u8 *ptr = (u8*)&buf;
+		int j;
+		vcpu_printf(vcpu, " 0x%16.16lx:", addr);
+		for (j = 0; j < sizeof(u64) ; j++)
+			vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+		vcpu_printf(vcpu, "\n");
+	}
+}
+
+#define IA32_DEBUGCTL_RESERVED_BITS 0xfffffffffffffe3cULL
+
+static int is_canonical(unsigned long addr)
+{
+       return  addr == ((long)addr << 16) >> 16;
+}
+
+int vm_entry_test_guest(struct kvm_vcpu *vcpu)
+{
+	unsigned long cr0;
+	unsigned long cr4;
+	unsigned long cr3;
+	unsigned long dr7;
+	u64 ia32_debugctl;
+	unsigned long sysenter_esp;
+	unsigned long sysenter_eip;
+	unsigned long rflags;
+
+	int long_mode;
+	int virtual8086;
+
+	#define RFLAGS_VM (1 << 17)
+	#define RFLAGS_RF (1 << 9)
+
+
+	#define VIR8086_SEG_BASE_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_BASE) != \
+		    (unsigned long)vmcs_read16(GUEST_##seg##_SELECTOR) << 4) {\
+			vcpu_printf(vcpu, "%s: "#seg" base 0x%lx in "\
+				   "virtual8086 is not "#seg" selector 0x%x"\
+				   " shifted right 4 bits\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE),\
+			   vmcs_read16(GUEST_##seg##_SELECTOR));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_LIMIT_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_LIMIT) != 0x0ffff) { \
+			vcpu_printf(vcpu, "%s: "#seg" limit 0x%lx in "\
+				   "virtual8086 is not 0xffff\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_LIMIT));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_AR_TEST(seg)\
+		if (vmcs_read32(GUEST_##seg##_AR_BYTES) != 0x0f3) { \
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x in "\
+				   "virtual8086 is not 0xf3\n",\
+			   __FUNCTION__,\
+			   vmcs_read32(GUEST_##seg##_AR_BYTES));\
+			return 0;\
+		}
+
+
+	cr0 = vmcs_readl(GUEST_CR0);
+
+	if (!(cr0 & CR0_PG_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PG is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_PE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_NE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, NE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_WP_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, WP is not set\n",
+			   __FUNCTION__, cr0);
+	}
+
+	cr4 = vmcs_readl(GUEST_CR4);
+
+	if (!(cr4 & CR4_VMXE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, VMXE is not set\n",
+			   __FUNCTION__, cr4);
+		return 0;
+	}
+
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, PAE is not set\n",
+			   __FUNCTION__, cr4);
+	}
+
+	ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
+
+	if (ia32_debugctl & IA32_DEBUGCTL_RESERVED_BITS ) {
+		vcpu_printf(vcpu, "%s: ia32_debugctl 0x%llx, reserve bits\n",
+			   __FUNCTION__, ia32_debugctl);
+		return 0;
+	}
+
+	long_mode = is_long_mode();
+
+	if (long_mode) {
+	}
+
+	if ( long_mode && !(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: long mode and not PAE\n",
+			   __FUNCTION__);
+		return 0;
+	}
+
+	cr3 = vmcs_readl(GUEST_CR3);
+
+	if (cr3 & CR3_L_MODE_RESEVED_BITS) {
+		vcpu_printf(vcpu, "%s: cr3 0x%lx, reserved bits\n",
+			   __FUNCTION__, cr3);
+		return 0;
+	}
+
+	if ( !long_mode && (cr4 & CR4_PAE_MASK)) {
+		/* check the 4 PDPTEs for reserved bits */
+		unsigned long pdpt_pfn = cr3 >> PAGE_SHIFT;
+		int i;
+		u64 pdpte;
+		unsigned offset = (cr3 & (PAGE_SIZE-1)) >> 5;
+		u64 *pdpt = kmap_atomic(pfn_to_page(pdpt_pfn), KM_USER0);
+
+		for (i = 0; i < 4; ++i) {
+			pdpte = pdpt[offset + i];
+			if ((pdpte & 1) && (pdpte & 0xfffffff0000001e6ull))
+				break;
+		}
+
+		kunmap_atomic(pdpt, KM_USER0);
+
+		if (i != 4) {
+			vcpu_printf(vcpu, "%s: pae cr3[%d] 0x%llx, reserved bits\n",
+				   __FUNCTION__, i, pdpte);
+			return 0;
+		}
+	}
+
+	dr7 = vmcs_readl(GUEST_DR7);
+
+	if (dr7 & ~((1ULL << 32) - 1)) {
+		vcpu_printf(vcpu, "%s: dr7 0x%lx, reserved bits\n",
+			   __FUNCTION__, dr7);
+		return 0;
+	}
+
+	sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
+
+	if (!is_canonical(sysenter_esp)) {
+		vcpu_printf(vcpu, "%s: sysenter_esp 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_esp);
+		return 0;
+	}
+
+	sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
+
+	if (!is_canonical(sysenter_eip)) {
+		vcpu_printf(vcpu, "%s: sysenter_eip 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_eip);
+		return 0;
+	}
+
+	rflags = vmcs_readl(GUEST_RFLAGS);
+	virtual8086 = rflags & RFLAGS_VM;
+
+
+	if (vmcs_read16(GUEST_TR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: tr selctor 0x%x, TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_TR_SELECTOR));
+	       return 0;
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	      vmcs_read16(GUEST_LDTR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: ldtr selctor 0x%x,"
+				     " is usable and TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_LDTR_SELECTOR));
+	       return 0;
+	}
+
+	if (!virtual8086 &&
+	    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) !=
+	    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK)) {
+		vcpu_printf(vcpu, "%s: ss selctor 0x%x cs selctor 0x%x,"
+				     " not same RPL\n",
+			   __FUNCTION__,
+			   vmcs_read16(GUEST_SS_SELECTOR),
+			   vmcs_read16(GUEST_CS_SELECTOR));
+		return 0;
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_BASE_TEST(CS);
+		VIR8086_SEG_BASE_TEST(SS);
+		VIR8086_SEG_BASE_TEST(DS);
+		VIR8086_SEG_BASE_TEST(ES);
+		VIR8086_SEG_BASE_TEST(FS);
+		VIR8086_SEG_BASE_TEST(GS);
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_TR_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_FS_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_GS_BASE)) ) {
+		vcpu_printf(vcpu, "%s: TR 0x%lx FS 0x%lx or GS 0x%lx base"
+				      " is not canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_TR_BASE),
+			   vmcs_readl(GUEST_FS_BASE),
+			   vmcs_readl(GUEST_GS_BASE));
+		return 0;
+
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	    !is_canonical(vmcs_readl(GUEST_LDTR_BASE))) {
+		vcpu_printf(vcpu, "%s: LDTR base 0x%lx, usable and is not"
+				      " canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_LDTR_BASE));
+		return 0;
+	}
+
+	if ((vmcs_readl(GUEST_CS_BASE) & ~((1ULL << 32) - 1))) {
+		vcpu_printf(vcpu, "%s: CS base 0x%lx, not all bits 63-32"
+				      " are zero\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_CS_BASE));
+		return 0;
+	}
+
+	#define SEG_BASE_TEST(seg)\
+	if ( !(vmcs_read32(GUEST_##seg##_AR_BYTES) & AR_UNUSABLE_MASK) &&\
+	     (vmcs_readl(GUEST_##seg##_BASE) & ~((1ULL << 32) - 1))) {\
+		vcpu_printf(vcpu, "%s: "#seg" base 0x%lx, is usable and not"\
+						" all bits 63-32 are zero\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE));\
+		return 0;\
+	}
+	SEG_BASE_TEST(SS);
+	SEG_BASE_TEST(DS);
+	SEG_BASE_TEST(ES);
+
+	if (virtual8086) {
+		VIR8086_SEG_LIMIT_TEST(CS);
+		VIR8086_SEG_LIMIT_TEST(SS);
+		VIR8086_SEG_LIMIT_TEST(DS);
+		VIR8086_SEG_LIMIT_TEST(ES);
+		VIR8086_SEG_LIMIT_TEST(FS);
+		VIR8086_SEG_LIMIT_TEST(GS);
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_AR_TEST(CS);
+		VIR8086_SEG_AR_TEST(SS);
+		VIR8086_SEG_AR_TEST(DS);
+		VIR8086_SEG_AR_TEST(ES);
+		VIR8086_SEG_AR_TEST(FS);
+		VIR8086_SEG_AR_TEST(GS);
+	} else {
+
+		u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
+		u32 ss_ar = vmcs_read32(GUEST_SS_AR_BYTES);
+		u32 tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
+		u32 ldtr_ar = vmcs_read32(GUEST_LDTR_AR_BYTES);
+
+		#define SEG_G_TEST(seg) {					\
+		u32 lim = vmcs_read32(GUEST_##seg##_LIMIT);		\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);		\
+		int err = 0;							\
+		if (((lim & ~PAGE_MASK) != ~PAGE_MASK) && (ar & AR_G_MASK))	\
+			err = 1;						\
+		if ((lim & ~((1u << 20) - 1)) && !(ar & AR_G_MASK))		\
+			err = 1;						\
+		if (err) {							\
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, G err. lim"	\
+							" is 0x%x\n",		\
+						   __FUNCTION__,		\
+						   ar, lim);			\
+			return 0;						\
+		}								\
+		}
+
+
+		if (!(cs_ar & AR_TYPE_ACCESSES_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, accesses is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_TYPE_CODE_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, code is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, type is sys\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 8 && (cs_ar & AR_TYPE_MASK) < 12 &&
+		    AR_DPL(cs_ar) !=
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 13 && (cs_ar & AR_TYPE_MASK) < 16 &&
+		    AR_DPL(cs_ar) >
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL greater than RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, not "
+						      "present\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if ((cs_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, reseved"
+						      " bits are set\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if (long_mode & (cs_ar & AR_L_MASK) && (cs_ar & AR_DB_MASK)) {
+			vcpu_printf(vcpu, "%s: CS AR 0x%x, DB and L are set"
+					      " in long mode\n",
+					   __FUNCTION__,
+					   cs_ar);
+			return 0;
+
+		}
+
+		SEG_G_TEST(CS);
+
+		if (!(ss_ar & AR_UNUSABLE_MASK)) {
+		    if ((ss_ar & AR_TYPE_MASK) != 3 &&
+			(ss_ar & AR_TYPE_MASK) != 7 ) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and type"
+					      " is not 3 or 7\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+
+		    if (!(ss_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and"
+					      " is sys\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+		    if (!(ss_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: SS AR 0x%x, usable"
+						      " and  not present\n",
+					   __FUNCTION__,
+					   ss_ar);
+				return 0;
+		    }
+
+		    if ((ss_ar & AR_RESERVD_MASK)) {
+					vcpu_printf(vcpu, "%s: SS AR 0x%x, reseved"
+							      " bits are set\n",
+						   __FUNCTION__,
+						   ss_ar);
+					return 0;
+		    }
+
+		    SEG_G_TEST(SS);
+
+		}
+
+		if (AR_DPL(ss_ar) !=
+		    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: SS AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   ss_ar);
+			return 0;
+		}
+
+		#define SEG_AR_TEST(seg) {\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);\
+		if (!(ar & AR_UNUSABLE_MASK)) {\
+			if (!(ar & AR_TYPE_ACCESSES_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"usable and not accesses\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_CODE_MASK) &&\
+			    !(ar & AR_TYPE_READABLE_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"code and not readable\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if (!(ar & AR_S_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " is sys\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_MASK) >= 0 && \
+			    (ar & AR_TYPE_MASK) < 12 && \
+			    AR_DPL(ar) < (vmcs_read16(GUEST_##seg##_SELECTOR) & \
+					  SELECTOR_RPL_MASK) ) {\
+				    vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+					      "DPL less than RPL\n",\
+					       __FUNCTION__,\
+					       ar);\
+				    return 0;\
+			}\
+			if (!(ar & AR_P_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " not present\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_RESERVD_MASK)) {\
+					vcpu_printf(vcpu, "%s: "#seg" AR"\
+							" 0x%x, reseved"\
+							" bits are set\n",\
+						   __FUNCTION__,\
+						   ar);\
+					return 0;\
+			}\
+			SEG_G_TEST(seg)\
+		}\
+		}
+
+#undef DS
+#undef ES
+#undef FS
+#undef GS
+
+		SEG_AR_TEST(DS);
+		SEG_AR_TEST(ES);
+		SEG_AR_TEST(FS);
+		SEG_AR_TEST(GS);
+
+		// TR test
+		if (long_mode) {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, long"
+						      " mode and not 64bit busy"
+						      " tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+		} else {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_32_TSS &&
+			    (tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_16_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, legacy"
+						      " mode and not 16/32bit "
+						      "busy tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+
+		}
+		if ((tr_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, S is set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		if (!(tr_ar & AR_P_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, P is not set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+
+		if ((tr_ar & (AR_RESERVD_MASK| AR_UNUSABLE_MASK))) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, reserved bit are"
+					      " set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		SEG_G_TEST(TR);
+
+		// TR test
+		if (!(ldtr_ar & AR_UNUSABLE_MASK)) {
+
+			if ((ldtr_ar & AR_TYPE_MASK) != AR_TYPE_LDT) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " bad type\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+			    return 0;
+			}
+
+			if ((ldtr_ar & AR_S_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " S is set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+
+			if (!(ldtr_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " P is not set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			if ((ldtr_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " reserved bit are  set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			SEG_G_TEST(LDTR);
+		}
+	}
+
+	// GDTR and IDTR
+
+
+	#define IDT_GDT_TEST(reg)\
+	if (!is_canonical(vmcs_readl(GUEST_##reg##_BASE))) {\
+		vcpu_printf(vcpu, "%s: "#reg" BASE 0x%lx, not canonical\n",\
+					   __FUNCTION__,\
+					   vmcs_readl(GUEST_##reg##_BASE));\
+		return 0;\
+	}\
+	if (vmcs_read32(GUEST_##reg##_LIMIT) >> 16) {\
+		vcpu_printf(vcpu, "%s: "#reg" LIMIT 0x%x, size err\n",\
+				   __FUNCTION__,\
+				   vmcs_read32(GUEST_##reg##_LIMIT));\
+		return 0;\
+	}\
+
+	IDT_GDT_TEST(GDTR);
+	IDT_GDT_TEST(IDTR);
+
+
+	// RIP
+
+	if ((!long_mode || !(vmcs_read32(GUEST_CS_AR_BYTES) & AR_L_MASK)) &&
+	    vmcs_readl(GUEST_RIP) & ~((1ULL << 32) - 1) ){
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, size err\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_RIP))) {
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, not canonical\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	// RFLAGS
+	#define RFLAGS_RESEVED_CLEAR_BITS\
+		(~((1ULL << 22) - 1) | (1ULL << 15) | (1ULL << 5) | (1ULL << 3))
+	#define RFLAGS_RESEVED_SET_BITS (1 << 1)
+
+	if ((rflags & RFLAGS_RESEVED_CLEAR_BITS) ||
+	    !(rflags & RFLAGS_RESEVED_SET_BITS)) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, reserved bits 0x%llx 0x%x\n",
+			   __FUNCTION__,
+			   rflags,
+			   RFLAGS_RESEVED_CLEAR_BITS,
+			   RFLAGS_RESEVED_SET_BITS);
+		return 0;
+	}
+
+	if (long_mode && virtual8086) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, vm and long mode\n",
+				   __FUNCTION__,
+				   rflags);
+		return 0;
+	}
+
+
+	if (!(rflags & RFLAGS_RF)) {
+		u32 vm_entry_info = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
+		if ((vm_entry_info & INTR_INFO_VALID_MASK) &&
+		    (vm_entry_info & INTR_INFO_INTR_TYPE_MASK) ==
+		    INTR_TYPE_EXT_INTR) {
+			vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, external"
+					      " interrupt and RF is clear\n",
+				   __FUNCTION__,
+				   rflags);
+			return 0;
+		}
+
+	}
+
+	// to be continued from Checks on Guest Non-Register State (22.3.1.5)
+	return 1;
+}
+
+static int check_fixed_bits(struct kvm_vcpu *vcpu, const char *reg,
+			    unsigned long cr,
+			    u32 msr_fixed_0, u32 msr_fixed_1)
+{
+	u64 fixed_bits_0, fixed_bits_1;
+
+	rdmsrl(msr_fixed_0, fixed_bits_0);
+	rdmsrl(msr_fixed_1, fixed_bits_1);
+	if ((cr & fixed_bits_0) != fixed_bits_0) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx unset\n",
+			   __FUNCTION__, reg, cr, fixed_bits_0);
+		return 0;
+	}
+	if ((~cr & ~fixed_bits_1) != ~fixed_bits_1) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx set\n",
+			   __FUNCTION__, reg, cr, ~fixed_bits_1);
+		return 0;
+	}
+	return 1;
+}
+
+static int phys_addr_width(void)
+{
+	unsigned eax, ebx, ecx, edx;
+
+	cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+	return eax & 0xff;
+}
+
+static int check_canonical(struct kvm_vcpu *vcpu, const char *name,
+			   unsigned long reg)
+{
+#ifdef __x86_64__
+	unsigned long x;
+
+	if (sizeof(reg) == 4)
+		return 1;
+	x = (long)reg >> 48;
+	if (!(x == 0 || x == ~0UL)) {
+		vcpu_printf(vcpu, "%s: %s (%lx) not canonical\n",
+			    __FUNCTION__, name, reg);
+		return 0;
+	}
+#endif
+	return 1;
+}
+
+static int check_selector(struct kvm_vcpu *vcpu, const char *name,
+			  int rpl_ti, int null,
+			  u16 sel)
+{
+	if (rpl_ti && (sel & 7)) {
+		vcpu_printf(vcpu, "%s: %s (%x) nonzero rpl or ti\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	if (null && !sel) {
+		vcpu_printf(vcpu, "%s: %s (%x) zero\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	return 1;
+}
+
+#define MSR_IA32_VMX_CR0_FIXED0 0x486
+#define MSR_IA32_VMX_CR0_FIXED1 0x487
+
+#define MSR_IA32_VMX_CR4_FIXED0 0x488
+#define MSR_IA32_VMX_CR4_FIXED1 0x489
+
+int vm_entry_test_host(struct kvm_vcpu *vcpu)
+{
+	int r = 0;
+	unsigned long cr0 = vmcs_readl(HOST_CR0);
+	unsigned long cr4 = vmcs_readl(HOST_CR4);
+	unsigned long cr3 = vmcs_readl(HOST_CR3);
+	int host_64;
+
+	host_64 = vmcs_read32(VM_EXIT_CONTROLS) & VM_EXIT_HOST_ADD_SPACE_SIZE;
+
+	/* 22.2.2 */
+	r &= check_fixed_bits(vcpu, "host cr0", cr0, MSR_IA32_VMX_CR0_FIXED0,
+			      MSR_IA32_VMX_CR0_FIXED1);
+
+	r &= check_fixed_bits(vcpu, "host cr0", cr4, MSR_IA32_VMX_CR4_FIXED0,
+			      MSR_IA32_VMX_CR4_FIXED1);
+	if ((u64)cr3 >> phys_addr_width()) {
+		vcpu_printf(vcpu, "%s: cr3 (%lx) vs phys addr width\n",
+			    __FUNCTION__, cr3);
+		r = 0;
+	}
+
+	r &= check_canonical(vcpu, "host ia32_sysenter_eip",
+			     vmcs_readl(HOST_IA32_SYSENTER_EIP));
+	r &= check_canonical(vcpu, "host ia32_sysenter_esp",
+			     vmcs_readl(HOST_IA32_SYSENTER_ESP));
+
+	/* 22.2.3 */
+	r &= check_selector(vcpu, "host cs", 1, 1,
+			    vmcs_read16(HOST_CS_SELECTOR));
+	r &= check_selector(vcpu, "host ss", 1, !host_64,
+			    vmcs_read16(HOST_SS_SELECTOR));
+	r &= check_selector(vcpu, "host ds", 1, 0,
+			    vmcs_read16(HOST_DS_SELECTOR));
+	r &= check_selector(vcpu, "host es", 1, 0,
+			    vmcs_read16(HOST_ES_SELECTOR));
+	r &= check_selector(vcpu, "host fs", 1, 0,
+			    vmcs_read16(HOST_FS_SELECTOR));
+	r &= check_selector(vcpu, "host gs", 1, 0,
+			    vmcs_read16(HOST_GS_SELECTOR));
+	r &= check_selector(vcpu, "host tr", 1, 1,
+			    vmcs_read16(HOST_TR_SELECTOR));
+
+#ifdef __x86_64__
+	r &= check_canonical(vcpu, "host fs base",
+			     vmcs_readl(HOST_FS_BASE));
+	r &= check_canonical(vcpu, "host gs base",
+			     vmcs_readl(HOST_GS_BASE));
+	r &= check_canonical(vcpu, "host gdtr base",
+			     vmcs_readl(HOST_GDTR_BASE));
+	r &= check_canonical(vcpu, "host idtr base",
+			     vmcs_readl(HOST_IDTR_BASE));
+#endif
+
+	/* 22.2.4 */
+#ifdef __x86_64__
+	if (!host_64) {
+		vcpu_printf(vcpu, "%s: vm exit controls: !64 bit host\n",
+			    __FUNCTION__);
+		r = 0;
+	}
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 (%lx): !pae\n",
+			    __FUNCTION__, cr4);
+		r = 0;
+	}
+	r &= check_canonical(vcpu, "host rip", vmcs_readl(HOST_RIP));
+#endif
+
+	return r;
+}
+
+int vm_entry_test(struct kvm_vcpu *vcpu)
+{
+	int rg, rh;
+
+	rg = vm_entry_test_guest(vcpu);
+	rh = vm_entry_test_host(vcpu);
+	return rg && rh;
+}
+
+void vmcs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ vmcs_dump ************************\n");
+	vcpu_printf(vcpu, "HOST_CR0 0x%lx\n", vmcs_readl(HOST_CR0));
+	vcpu_printf(vcpu, "HOST_CR3 0x%lx\n", vmcs_readl(HOST_CR3));
+	vcpu_printf(vcpu, "HOST_CR4 0x%lx\n", vmcs_readl(HOST_CR4));
+
+	vcpu_printf(vcpu, "HOST_TR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_TR_BASE 0x%lx\n", vmcs_readl(HOST_TR_BASE));
+	vcpu_printf(vcpu, "HOST_TR_LIMIT 0x%x\n", vmcs_read32(HOST_TR_LIMIT));
+
+	vcpu_printf(vcpu, "HOST_GDTR_BASE 0x%lx\n", vmcs_readl(HOST_GDTR_BASE));
+	vcpu_printf(vcpu, "HOST_GDTR_LIMIT 0x%x\n", vmcs_read32(HOST_GDTR_LIMIT));
+
+	vcpu_printf(vcpu, "HOST_LDTR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_LDTR_BASE 0x%lx\n", vmcs_readl(HOST_TR_BASE));
+	vcpu_printf(vcpu, "HOST_LDTR_LIMIT 0x%x\n", vmcs_read32(HOST_TR_LIMIT));
+
+	vcpu_printf(vcpu, "HOST_CS_SELECTOR 0x%x\n", vmcs_read16(HOST_CS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_DS_SELECTOR 0x%x\n", vmcs_read16(HOST_DS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_ES_SELECTOR 0x%x\n", vmcs_read16(HOST_ES_SELECTOR));
+	vcpu_printf(vcpu, "HOST_FS_SELECTOR 0x%x\n", vmcs_read16(HOST_FS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_GS_SELECTOR 0x%x\n", vmcs_read16(HOST_GS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_SS_SELECTOR 0x%x\n", vmcs_read16(HOST_SS_SELECTOR));
+
+
+	vcpu_printf(vcpu, "VM_ENTRY_CONTROLS 0x%x\n", vmcs_read32(VM_ENTRY_CONTROLS));
+
+	vcpu_printf(vcpu, "GUEST_CR0 0x%lx\n", vmcs_readl(GUEST_CR0));
+	vcpu_printf(vcpu, "GUEST_CR3 0x%lx\n", vmcs_readl(GUEST_CR3));
+	vcpu_printf(vcpu, "GUEST_CR4 0x%lx\n", vmcs_readl(GUEST_CR4));
+
+	vcpu_printf(vcpu, "GUEST_SYSENTER_ESP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_ESP));
+	vcpu_printf(vcpu, "GUEST_SYSENTER_EIP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_EIP));
+
+
+	vcpu_printf(vcpu, "GUEST_IA32_DEBUGCTL 0x%llx\n", vmcs_read64(GUEST_IA32_DEBUGCTL));
+	vcpu_printf(vcpu, "GUEST_DR7 0x%lx\n", vmcs_readl(GUEST_DR7));
+
+	vcpu_printf(vcpu, "GUEST_RFLAGS 0x%lx\n", vmcs_readl(GUEST_RFLAGS));
+	vcpu_printf(vcpu, "GUEST_RIP 0x%lx\n", vmcs_readl(GUEST_RIP));
+
+	vcpu_printf(vcpu, "GUEST_CS_SELECTOR 0x%x\n", vmcs_read16(GUEST_CS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_DS_SELECTOR 0x%x\n", vmcs_read16(GUEST_DS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_ES_SELECTOR 0x%x\n", vmcs_read16(GUEST_ES_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_FS_SELECTOR 0x%x\n", vmcs_read16(GUEST_FS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_GS_SELECTOR 0x%x\n", vmcs_read16(GUEST_GS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_SS_SELECTOR 0x%x\n", vmcs_read16(GUEST_SS_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_TR_SELECTOR 0x%x\n", vmcs_read16(GUEST_TR_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_LDTR_SELECTOR 0x%x\n", vmcs_read16(GUEST_LDTR_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_CS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_CS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_DS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_DS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_ES_AR_BYTES 0x%x\n", vmcs_read32(GUEST_ES_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_FS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_FS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_GS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_GS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_SS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_SS_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_LDTR_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_TR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_TR_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_CS_BASE 0x%lx\n", vmcs_readl(GUEST_CS_BASE));
+	vcpu_printf(vcpu, "GUEST_DS_BASE 0x%lx\n", vmcs_readl(GUEST_DS_BASE));
+	vcpu_printf(vcpu, "GUEST_ES_BASE 0x%lx\n", vmcs_readl(GUEST_ES_BASE));
+	vcpu_printf(vcpu, "GUEST_FS_BASE 0x%lx\n", vmcs_readl(GUEST_FS_BASE));
+	vcpu_printf(vcpu, "GUEST_GS_BASE 0x%lx\n", vmcs_readl(GUEST_GS_BASE));
+	vcpu_printf(vcpu, "GUEST_SS_BASE 0x%lx\n", vmcs_readl(GUEST_SS_BASE));
+
+
+	vcpu_printf(vcpu, "GUEST_LDTR_BASE 0x%lx\n", vmcs_readl(GUEST_LDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_TR_BASE 0x%lx\n", vmcs_readl(GUEST_TR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_CS_LIMIT 0x%x\n", vmcs_read32(GUEST_CS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_DS_LIMIT 0x%x\n", vmcs_read32(GUEST_DS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_ES_LIMIT 0x%x\n", vmcs_read32(GUEST_ES_LIMIT));
+	vcpu_printf(vcpu, "GUEST_FS_LIMIT 0x%x\n", vmcs_read32(GUEST_FS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_GS_LIMIT 0x%x\n", vmcs_read32(GUEST_GS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_SS_LIMIT 0x%x\n", vmcs_read32(GUEST_SS_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_LDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_TR_LIMIT 0x%x\n", vmcs_read32(GUEST_TR_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_BASE 0x%lx\n", vmcs_readl(GUEST_GDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_IDTR_BASE 0x%lx\n", vmcs_readl(GUEST_IDTR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_GDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_IDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_IDTR_LIMIT));
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void regs_dump(struct kvm_vcpu *vcpu)
+{
+	#define REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vcpu->regs[VCPU_REGS_##reg])
+	#define VMCS_REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vmcs_readl(GUEST_##reg))
+
+	vcpu_printf(vcpu, "************************ regs_dump ************************\n");
+	REG_DUMP(RAX);
+	REG_DUMP(RBX);
+	REG_DUMP(RCX);
+	REG_DUMP(RDX);
+	REG_DUMP(RSP);
+	REG_DUMP(RBP);
+	REG_DUMP(RSI);
+	REG_DUMP(RDI);
+	REG_DUMP(R8);
+	REG_DUMP(R9);
+	REG_DUMP(R10);
+	REG_DUMP(R11);
+	REG_DUMP(R12);
+	REG_DUMP(R13);
+	REG_DUMP(R14);
+	REG_DUMP(R15);
+
+	VMCS_REG_DUMP(RSP);
+	VMCS_REG_DUMP(RIP);
+	VMCS_REG_DUMP(RFLAGS);
+
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void sregs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ sregs_dump ************************\n");
+	vcpu_printf(vcpu, "cr0 = 0x%lx\n", guest_cr0());
+	vcpu_printf(vcpu, "cr2 = 0x%lx\n", vcpu->cr2);
+	vcpu_printf(vcpu, "cr3 = 0x%lx\n", vcpu->cr3);
+	vcpu_printf(vcpu, "cr4 = 0x%lx\n", guest_cr4());
+	vcpu_printf(vcpu, "cr8 = 0x%lx\n", vcpu->cr8);
+	vcpu_printf(vcpu, "shadow_efer = 0x%llx\n", vcpu->shadow_efer);
+	vmcs_dump(vcpu);
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+#endif
+
Index: linux-2.6/drivers/kvm/debug.h
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.h
@@ -0,0 +1,21 @@
+#ifndef __KVM_DEBUG_H
+#define __KVM_DEBUG_H
+
+#ifdef KVM_DEBUG
+
+void show_msrs(struct kvm_vcpu *vcpu);
+
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq);
+void show_page(struct kvm_vcpu *vcpu, gva_t addr);
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr);
+void show_code(struct kvm_vcpu *vcpu);
+int vm_entry_test(struct kvm_vcpu *vcpu);
+
+void vmcs_dump(struct kvm_vcpu *vcpu);
+void regs_dump(struct kvm_vcpu *vcpu);
+void sregs_dump(struct kvm_vcpu *vcpu);
+
+#endif
+
+#endif
Index: linux-2.6/drivers/kvm/kvm.h
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm.h
+++ linux-2.6/drivers/kvm/kvm.h
@@ -9,6 +9,8 @@
 
 #include "vmx.h"
 
+#define KVM_DEBUG 1
+
 #define CR0_PE_MASK (1ULL << 0)
 #define CR0_TS_MASK (1ULL << 3)
 #define CR0_NE_MASK (1ULL << 5)
Index: linux-2.6/drivers/kvm/kvm_main.c
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm_main.c
+++ linux-2.6/drivers/kvm/kvm_main.c
@@ -33,6 +33,7 @@
 
 #include "vmx.h"
 #include "x86_emulate.h"
+#include "debug.h"
 
 MODULE_AUTHOR("Qumranet");
 MODULE_LICENSE("GPL");
@@ -1107,6 +1108,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 	int nr_good_msrs;
 
 
+	printk("*** vcpu_setup begin\n");
+	vmcs_dump(vcpu);
+
 	if (!init_rmode_tss(vcpu->kvm)) {
 		ret = 0;
 		goto out;
@@ -1303,6 +1307,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 
 	ret = kvm_mmu_init(vcpu);
 
+	printk("*** vcpu_setup end\n");
+	vmcs_dump(vcpu);
+
 	return ret;
 
 out_free_guest_msrs:
@@ -2618,6 +2625,9 @@ again:
 	fx_save(vcpu->host_fx_image);
 	fx_restore(vcpu->guest_fx_image);
 
+	printk("*** pre launch\n");
+	vmcs_dump(vcpu);
+
 	save_msrs(vcpu->host_msrs, vcpu->nmsrs);
 	load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
 
@@ -2740,6 +2750,9 @@ again:
 		[cr2]"i"(offsetof(struct kvm_vcpu, cr2))
 	      : "cc", "memory" );
 
+	printk("*** post launch\n");
+	vmcs_dump(vcpu);
+
 	++kvm_stat.exits;
 
 	save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);

[-- Attachment #3: Type: text/plain, Size: 373 bytes --]

-------------------------------------------------------------------------
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[-- Attachment #4: Type: text/plain, Size: 186 bytes --]

_______________________________________________
kvm-devel mailing list
kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
https://lists.sourceforge.net/lists/listinfo/kvm-devel

Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

On Tuesday 07 November 2006 13:31, Avi Kivity wrote:
> Hesse, Christian wrote:
> >> Then, please apply the attached patch.  You will need serial console or
> >> netconsole, and to
> >>
> >>    echo 9 > /proc/sysrq-trigger
> >>
> >> before launching the VM.
> >
> > There is no patch attached to this mail...
>
> Sorry, attaching now.

There are some undefined values in your code:

/usr/src/kvm-module/debug.c: In function 'vmcs_dump':
/usr/src/kvm-module/debug.c:924: error: 'HOST_TR_LIMIT' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:924: error: (Each undeclared identifier is 
reported only once
/usr/src/kvm-module/debug.c:924: error: for each function it appears in.)
/usr/src/kvm-module/debug.c:927: error: 'HOST_GDTR_LIMIT' undeclared (first 
use in this function)
/usr/src/kvm-module/debug.c: In function 'regs_dump':
/usr/src/kvm-module/debug.c:1022: error: 'VCPU_REGS_R8' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1023: error: 'VCPU_REGS_R9' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1024: error: 'VCPU_REGS_R10' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1025: error: 'VCPU_REGS_R11' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1026: error: 'VCPU_REGS_R12' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1027: error: 'VCPU_REGS_R13' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1028: error: 'VCPU_REGS_R14' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1029: error: 'VCPU_REGS_R15' undeclared (first use 
in this function)

> >> BTW, what OS are you trying to run in the guest?
> >
> > I try to boot a Windows XP SP2 install CD.
>
> Ok.  kvm isn't really able to complete the install (Windows will
> bluescreen) but it shouldn't lock up either.
>
> (you can install with qemu and run with kvm

I already do have a working qemu installation (that freezes the system as 
well, that was the first I tried to boot).
-- 
Regards,
Chris

-------------------------------------------------------------------------
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 716 bytes --]

Hesse, Christian wrote:
> On Tuesday 07 November 2006 13:31, Avi Kivity wrote:
>   
>> Hesse, Christian wrote:
>>     
>>>> Then, please apply the attached patch.  You will need serial console or
>>>> netconsole, and to
>>>>
>>>>    echo 9 > /proc/sysrq-trigger
>>>>
>>>> before launching the VM.
>>>>         
>>> There is no patch attached to this mail...
>>>       
>> Sorry, attaching now.
>>     
>
> There are some undefined values in your code:
>
> /usr/src/kvm-module/debug.c: In function 'vmcs_dump':
> /usr/src/kvm-module/debug.c:924: error: 'HOST_TR_LIMIT' undeclared (first use 
> in this function)
>   

Sorry, refreshed patch attached.

-- 
error compiling committee.c: too many arguments to function


[-- Attachment #2: kvm-debug.patch --]
[-- Type: text/x-patch, Size: 31493 bytes --]

Index: linux-2.6/drivers/kvm/debug.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.c
@@ -0,0 +1,1049 @@
+/*
+ * Kernel-based Virtual Machine driver for Linux
+ *
+ * This module enables machines with Intel VT-x extensions to run virtual
+ * machines without emulation or binary translation.
+ *
+ * Debug support
+ *
+ * Copyright (C) 2006 Qumranet, Inc.
+ *
+ * Authors:
+ *   Yaniv Kamay  <yaniv-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *   Avi Kivity   <avi-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *
+ */
+
+#include <linux/highmem.h>
+
+#include <linux/kvm.h>
+#include "kvm.h"
+#include "debug.h"
+
+#ifdef KVM_DEBUG
+
+static const char *vmx_msr_name[] = {
+	"MSR_EFER", "MSR_STAR", "MSR_CSTAR",
+	"MSR_KERNEL_GS_BASE", "MSR_SYSCALL_MASK", "MSR_LSTAR"
+};
+
+#define NR_VMX_MSR (sizeof(vmx_msr_name) / sizeof(char*))
+
+void show_msrs(struct kvm_vcpu *vcpu)
+{
+	int i;
+
+	for (i = 0; i < NR_VMX_MSR; ++i) {
+		vcpu_printf(vcpu, "%s: %s=0x%llx\n",
+		       __FUNCTION__,
+		       vmx_msr_name[i],
+		       vcpu->guest_msrs[i].data);
+	}
+}
+
+void show_code(struct kvm_vcpu *vcpu)
+{
+	gva_t rip = vmcs_readl(GUEST_RIP);
+	u8 code[50];
+	char buf[30 + 3 * sizeof code];
+	int i;
+
+	if (!is_long_mode())
+		rip += vmcs_readl(GUEST_CS_BASE);
+
+	kvm_read_guest(vcpu, rip, sizeof code, code);
+	for (i = 0; i < sizeof code; ++i)
+		sprintf(buf + i * 3, " %02x", code[i]);
+	vcpu_printf(vcpu, "code: %lx%s\n", rip, buf);
+}
+
+struct gate_struct {
+	u16 offset_low;
+	u16 segment;
+	unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
+	u16 offset_middle;
+	u32 offset_high;
+	u32 zero1;
+} __attribute__((packed));
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq)
+{
+	unsigned long idt_base = vmcs_readl(GUEST_IDTR_BASE);
+	unsigned long idt_limit = vmcs_readl(GUEST_IDTR_LIMIT);
+	struct gate_struct gate;
+
+	if (!is_long_mode())
+		vcpu_printf(vcpu, "%s: not in long mode\n", __FUNCTION__);
+
+	if (!is_long_mode() || idt_limit < irq * sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+
+	if (kvm_read_guest(vcpu, idt_base + irq * sizeof(gate), sizeof(gate), &gate) != sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+	vcpu_printf(vcpu, "%s: 0x%x handler 0x%llx\n",
+		   __FUNCTION__,
+		   irq,
+		   ((u64)gate.offset_high << 32) |
+		   ((u64)gate.offset_middle << 16) |
+		   gate.offset_low);
+}
+
+void show_page(struct kvm_vcpu *vcpu,
+			     gva_t addr)
+{
+	u64 *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	if (!buf)
+		return;
+
+	addr &= PAGE_MASK;
+	if (kvm_read_guest(vcpu, addr, PAGE_SIZE, buf)) {
+		int i;
+		for (i = 0; i <  PAGE_SIZE / sizeof(u64) ; i++) {
+			u8 *ptr = (u8*)&buf[i];
+			int j;
+			vcpu_printf(vcpu, " 0x%16.16lx:",
+				   addr + i * sizeof(u64));
+			for (j = 0; j < sizeof(u64) ; j++)
+				vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+			vcpu_printf(vcpu, "\n");
+		}
+	}
+	kfree(buf);
+}
+
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr)
+{
+	u64 buf;
+
+	if (kvm_read_guest(vcpu, addr, sizeof(u64), &buf) == sizeof(u64)) {
+		u8 *ptr = (u8*)&buf;
+		int j;
+		vcpu_printf(vcpu, " 0x%16.16lx:", addr);
+		for (j = 0; j < sizeof(u64) ; j++)
+			vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+		vcpu_printf(vcpu, "\n");
+	}
+}
+
+#define IA32_DEBUGCTL_RESERVED_BITS 0xfffffffffffffe3cULL
+
+static int is_canonical(unsigned long addr)
+{
+       return  addr == ((long)addr << 16) >> 16;
+}
+
+int vm_entry_test_guest(struct kvm_vcpu *vcpu)
+{
+	unsigned long cr0;
+	unsigned long cr4;
+	unsigned long cr3;
+	unsigned long dr7;
+	u64 ia32_debugctl;
+	unsigned long sysenter_esp;
+	unsigned long sysenter_eip;
+	unsigned long rflags;
+
+	int long_mode;
+	int virtual8086;
+
+	#define RFLAGS_VM (1 << 17)
+	#define RFLAGS_RF (1 << 9)
+
+
+	#define VIR8086_SEG_BASE_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_BASE) != \
+		    (unsigned long)vmcs_read16(GUEST_##seg##_SELECTOR) << 4) {\
+			vcpu_printf(vcpu, "%s: "#seg" base 0x%lx in "\
+				   "virtual8086 is not "#seg" selector 0x%x"\
+				   " shifted right 4 bits\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE),\
+			   vmcs_read16(GUEST_##seg##_SELECTOR));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_LIMIT_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_LIMIT) != 0x0ffff) { \
+			vcpu_printf(vcpu, "%s: "#seg" limit 0x%lx in "\
+				   "virtual8086 is not 0xffff\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_LIMIT));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_AR_TEST(seg)\
+		if (vmcs_read32(GUEST_##seg##_AR_BYTES) != 0x0f3) { \
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x in "\
+				   "virtual8086 is not 0xf3\n",\
+			   __FUNCTION__,\
+			   vmcs_read32(GUEST_##seg##_AR_BYTES));\
+			return 0;\
+		}
+
+
+	cr0 = vmcs_readl(GUEST_CR0);
+
+	if (!(cr0 & CR0_PG_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PG is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_PE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_NE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, NE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_WP_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, WP is not set\n",
+			   __FUNCTION__, cr0);
+	}
+
+	cr4 = vmcs_readl(GUEST_CR4);
+
+	if (!(cr4 & CR4_VMXE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, VMXE is not set\n",
+			   __FUNCTION__, cr4);
+		return 0;
+	}
+
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, PAE is not set\n",
+			   __FUNCTION__, cr4);
+	}
+
+	ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
+
+	if (ia32_debugctl & IA32_DEBUGCTL_RESERVED_BITS ) {
+		vcpu_printf(vcpu, "%s: ia32_debugctl 0x%llx, reserve bits\n",
+			   __FUNCTION__, ia32_debugctl);
+		return 0;
+	}
+
+	long_mode = is_long_mode();
+
+	if (long_mode) {
+	}
+
+	if ( long_mode && !(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: long mode and not PAE\n",
+			   __FUNCTION__);
+		return 0;
+	}
+
+	cr3 = vmcs_readl(GUEST_CR3);
+
+	if (cr3 & CR3_L_MODE_RESEVED_BITS) {
+		vcpu_printf(vcpu, "%s: cr3 0x%lx, reserved bits\n",
+			   __FUNCTION__, cr3);
+		return 0;
+	}
+
+	if ( !long_mode && (cr4 & CR4_PAE_MASK)) {
+		/* check the 4 PDPTEs for reserved bits */
+		unsigned long pdpt_pfn = cr3 >> PAGE_SHIFT;
+		int i;
+		u64 pdpte;
+		unsigned offset = (cr3 & (PAGE_SIZE-1)) >> 5;
+		u64 *pdpt = kmap_atomic(pfn_to_page(pdpt_pfn), KM_USER0);
+
+		for (i = 0; i < 4; ++i) {
+			pdpte = pdpt[offset + i];
+			if ((pdpte & 1) && (pdpte & 0xfffffff0000001e6ull))
+				break;
+		}
+
+		kunmap_atomic(pdpt, KM_USER0);
+
+		if (i != 4) {
+			vcpu_printf(vcpu, "%s: pae cr3[%d] 0x%llx, reserved bits\n",
+				   __FUNCTION__, i, pdpte);
+			return 0;
+		}
+	}
+
+	dr7 = vmcs_readl(GUEST_DR7);
+
+	if (dr7 & ~((1ULL << 32) - 1)) {
+		vcpu_printf(vcpu, "%s: dr7 0x%lx, reserved bits\n",
+			   __FUNCTION__, dr7);
+		return 0;
+	}
+
+	sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
+
+	if (!is_canonical(sysenter_esp)) {
+		vcpu_printf(vcpu, "%s: sysenter_esp 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_esp);
+		return 0;
+	}
+
+	sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
+
+	if (!is_canonical(sysenter_eip)) {
+		vcpu_printf(vcpu, "%s: sysenter_eip 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_eip);
+		return 0;
+	}
+
+	rflags = vmcs_readl(GUEST_RFLAGS);
+	virtual8086 = rflags & RFLAGS_VM;
+
+
+	if (vmcs_read16(GUEST_TR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: tr selctor 0x%x, TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_TR_SELECTOR));
+	       return 0;
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	      vmcs_read16(GUEST_LDTR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: ldtr selctor 0x%x,"
+				     " is usable and TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_LDTR_SELECTOR));
+	       return 0;
+	}
+
+	if (!virtual8086 &&
+	    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) !=
+	    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK)) {
+		vcpu_printf(vcpu, "%s: ss selctor 0x%x cs selctor 0x%x,"
+				     " not same RPL\n",
+			   __FUNCTION__,
+			   vmcs_read16(GUEST_SS_SELECTOR),
+			   vmcs_read16(GUEST_CS_SELECTOR));
+		return 0;
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_BASE_TEST(CS);
+		VIR8086_SEG_BASE_TEST(SS);
+		VIR8086_SEG_BASE_TEST(DS);
+		VIR8086_SEG_BASE_TEST(ES);
+		VIR8086_SEG_BASE_TEST(FS);
+		VIR8086_SEG_BASE_TEST(GS);
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_TR_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_FS_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_GS_BASE)) ) {
+		vcpu_printf(vcpu, "%s: TR 0x%lx FS 0x%lx or GS 0x%lx base"
+				      " is not canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_TR_BASE),
+			   vmcs_readl(GUEST_FS_BASE),
+			   vmcs_readl(GUEST_GS_BASE));
+		return 0;
+
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	    !is_canonical(vmcs_readl(GUEST_LDTR_BASE))) {
+		vcpu_printf(vcpu, "%s: LDTR base 0x%lx, usable and is not"
+				      " canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_LDTR_BASE));
+		return 0;
+	}
+
+	if ((vmcs_readl(GUEST_CS_BASE) & ~((1ULL << 32) - 1))) {
+		vcpu_printf(vcpu, "%s: CS base 0x%lx, not all bits 63-32"
+				      " are zero\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_CS_BASE));
+		return 0;
+	}
+
+	#define SEG_BASE_TEST(seg)\
+	if ( !(vmcs_read32(GUEST_##seg##_AR_BYTES) & AR_UNUSABLE_MASK) &&\
+	     (vmcs_readl(GUEST_##seg##_BASE) & ~((1ULL << 32) - 1))) {\
+		vcpu_printf(vcpu, "%s: "#seg" base 0x%lx, is usable and not"\
+						" all bits 63-32 are zero\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE));\
+		return 0;\
+	}
+	SEG_BASE_TEST(SS);
+	SEG_BASE_TEST(DS);
+	SEG_BASE_TEST(ES);
+
+	if (virtual8086) {
+		VIR8086_SEG_LIMIT_TEST(CS);
+		VIR8086_SEG_LIMIT_TEST(SS);
+		VIR8086_SEG_LIMIT_TEST(DS);
+		VIR8086_SEG_LIMIT_TEST(ES);
+		VIR8086_SEG_LIMIT_TEST(FS);
+		VIR8086_SEG_LIMIT_TEST(GS);
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_AR_TEST(CS);
+		VIR8086_SEG_AR_TEST(SS);
+		VIR8086_SEG_AR_TEST(DS);
+		VIR8086_SEG_AR_TEST(ES);
+		VIR8086_SEG_AR_TEST(FS);
+		VIR8086_SEG_AR_TEST(GS);
+	} else {
+
+		u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
+		u32 ss_ar = vmcs_read32(GUEST_SS_AR_BYTES);
+		u32 tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
+		u32 ldtr_ar = vmcs_read32(GUEST_LDTR_AR_BYTES);
+
+		#define SEG_G_TEST(seg) {					\
+		u32 lim = vmcs_read32(GUEST_##seg##_LIMIT);		\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);		\
+		int err = 0;							\
+		if (((lim & ~PAGE_MASK) != ~PAGE_MASK) && (ar & AR_G_MASK))	\
+			err = 1;						\
+		if ((lim & ~((1u << 20) - 1)) && !(ar & AR_G_MASK))		\
+			err = 1;						\
+		if (err) {							\
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, G err. lim"	\
+							" is 0x%x\n",		\
+						   __FUNCTION__,		\
+						   ar, lim);			\
+			return 0;						\
+		}								\
+		}
+
+
+		if (!(cs_ar & AR_TYPE_ACCESSES_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, accesses is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_TYPE_CODE_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, code is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, type is sys\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 8 && (cs_ar & AR_TYPE_MASK) < 12 &&
+		    AR_DPL(cs_ar) !=
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 13 && (cs_ar & AR_TYPE_MASK) < 16 &&
+		    AR_DPL(cs_ar) >
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL greater than RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, not "
+						      "present\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if ((cs_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, reseved"
+						      " bits are set\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if (long_mode & (cs_ar & AR_L_MASK) && (cs_ar & AR_DB_MASK)) {
+			vcpu_printf(vcpu, "%s: CS AR 0x%x, DB and L are set"
+					      " in long mode\n",
+					   __FUNCTION__,
+					   cs_ar);
+			return 0;
+
+		}
+
+		SEG_G_TEST(CS);
+
+		if (!(ss_ar & AR_UNUSABLE_MASK)) {
+		    if ((ss_ar & AR_TYPE_MASK) != 3 &&
+			(ss_ar & AR_TYPE_MASK) != 7 ) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and type"
+					      " is not 3 or 7\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+
+		    if (!(ss_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and"
+					      " is sys\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+		    if (!(ss_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: SS AR 0x%x, usable"
+						      " and  not present\n",
+					   __FUNCTION__,
+					   ss_ar);
+				return 0;
+		    }
+
+		    if ((ss_ar & AR_RESERVD_MASK)) {
+					vcpu_printf(vcpu, "%s: SS AR 0x%x, reseved"
+							      " bits are set\n",
+						   __FUNCTION__,
+						   ss_ar);
+					return 0;
+		    }
+
+		    SEG_G_TEST(SS);
+
+		}
+
+		if (AR_DPL(ss_ar) !=
+		    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: SS AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   ss_ar);
+			return 0;
+		}
+
+		#define SEG_AR_TEST(seg) {\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);\
+		if (!(ar & AR_UNUSABLE_MASK)) {\
+			if (!(ar & AR_TYPE_ACCESSES_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"usable and not accesses\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_CODE_MASK) &&\
+			    !(ar & AR_TYPE_READABLE_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"code and not readable\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if (!(ar & AR_S_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " is sys\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_MASK) >= 0 && \
+			    (ar & AR_TYPE_MASK) < 12 && \
+			    AR_DPL(ar) < (vmcs_read16(GUEST_##seg##_SELECTOR) & \
+					  SELECTOR_RPL_MASK) ) {\
+				    vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+					      "DPL less than RPL\n",\
+					       __FUNCTION__,\
+					       ar);\
+				    return 0;\
+			}\
+			if (!(ar & AR_P_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " not present\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_RESERVD_MASK)) {\
+					vcpu_printf(vcpu, "%s: "#seg" AR"\
+							" 0x%x, reseved"\
+							" bits are set\n",\
+						   __FUNCTION__,\
+						   ar);\
+					return 0;\
+			}\
+			SEG_G_TEST(seg)\
+		}\
+		}
+
+#undef DS
+#undef ES
+#undef FS
+#undef GS
+
+		SEG_AR_TEST(DS);
+		SEG_AR_TEST(ES);
+		SEG_AR_TEST(FS);
+		SEG_AR_TEST(GS);
+
+		// TR test
+		if (long_mode) {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, long"
+						      " mode and not 64bit busy"
+						      " tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+		} else {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_32_TSS &&
+			    (tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_16_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, legacy"
+						      " mode and not 16/32bit "
+						      "busy tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+
+		}
+		if ((tr_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, S is set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		if (!(tr_ar & AR_P_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, P is not set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+
+		if ((tr_ar & (AR_RESERVD_MASK| AR_UNUSABLE_MASK))) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, reserved bit are"
+					      " set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		SEG_G_TEST(TR);
+
+		// TR test
+		if (!(ldtr_ar & AR_UNUSABLE_MASK)) {
+
+			if ((ldtr_ar & AR_TYPE_MASK) != AR_TYPE_LDT) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " bad type\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+			    return 0;
+			}
+
+			if ((ldtr_ar & AR_S_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " S is set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+
+			if (!(ldtr_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " P is not set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			if ((ldtr_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " reserved bit are  set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			SEG_G_TEST(LDTR);
+		}
+	}
+
+	// GDTR and IDTR
+
+
+	#define IDT_GDT_TEST(reg)\
+	if (!is_canonical(vmcs_readl(GUEST_##reg##_BASE))) {\
+		vcpu_printf(vcpu, "%s: "#reg" BASE 0x%lx, not canonical\n",\
+					   __FUNCTION__,\
+					   vmcs_readl(GUEST_##reg##_BASE));\
+		return 0;\
+	}\
+	if (vmcs_read32(GUEST_##reg##_LIMIT) >> 16) {\
+		vcpu_printf(vcpu, "%s: "#reg" LIMIT 0x%x, size err\n",\
+				   __FUNCTION__,\
+				   vmcs_read32(GUEST_##reg##_LIMIT));\
+		return 0;\
+	}\
+
+	IDT_GDT_TEST(GDTR);
+	IDT_GDT_TEST(IDTR);
+
+
+	// RIP
+
+	if ((!long_mode || !(vmcs_read32(GUEST_CS_AR_BYTES) & AR_L_MASK)) &&
+	    vmcs_readl(GUEST_RIP) & ~((1ULL << 32) - 1) ){
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, size err\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_RIP))) {
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, not canonical\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	// RFLAGS
+	#define RFLAGS_RESEVED_CLEAR_BITS\
+		(~((1ULL << 22) - 1) | (1ULL << 15) | (1ULL << 5) | (1ULL << 3))
+	#define RFLAGS_RESEVED_SET_BITS (1 << 1)
+
+	if ((rflags & RFLAGS_RESEVED_CLEAR_BITS) ||
+	    !(rflags & RFLAGS_RESEVED_SET_BITS)) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, reserved bits 0x%llx 0x%x\n",
+			   __FUNCTION__,
+			   rflags,
+			   RFLAGS_RESEVED_CLEAR_BITS,
+			   RFLAGS_RESEVED_SET_BITS);
+		return 0;
+	}
+
+	if (long_mode && virtual8086) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, vm and long mode\n",
+				   __FUNCTION__,
+				   rflags);
+		return 0;
+	}
+
+
+	if (!(rflags & RFLAGS_RF)) {
+		u32 vm_entry_info = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
+		if ((vm_entry_info & INTR_INFO_VALID_MASK) &&
+		    (vm_entry_info & INTR_INFO_INTR_TYPE_MASK) ==
+		    INTR_TYPE_EXT_INTR) {
+			vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, external"
+					      " interrupt and RF is clear\n",
+				   __FUNCTION__,
+				   rflags);
+			return 0;
+		}
+
+	}
+
+	// to be continued from Checks on Guest Non-Register State (22.3.1.5)
+	return 1;
+}
+
+static int check_fixed_bits(struct kvm_vcpu *vcpu, const char *reg,
+			    unsigned long cr,
+			    u32 msr_fixed_0, u32 msr_fixed_1)
+{
+	u64 fixed_bits_0, fixed_bits_1;
+
+	rdmsrl(msr_fixed_0, fixed_bits_0);
+	rdmsrl(msr_fixed_1, fixed_bits_1);
+	if ((cr & fixed_bits_0) != fixed_bits_0) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx unset\n",
+			   __FUNCTION__, reg, cr, fixed_bits_0);
+		return 0;
+	}
+	if ((~cr & ~fixed_bits_1) != ~fixed_bits_1) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx set\n",
+			   __FUNCTION__, reg, cr, ~fixed_bits_1);
+		return 0;
+	}
+	return 1;
+}
+
+static int phys_addr_width(void)
+{
+	unsigned eax, ebx, ecx, edx;
+
+	cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+	return eax & 0xff;
+}
+
+static int check_canonical(struct kvm_vcpu *vcpu, const char *name,
+			   unsigned long reg)
+{
+#ifdef __x86_64__
+	unsigned long x;
+
+	if (sizeof(reg) == 4)
+		return 1;
+	x = (long)reg >> 48;
+	if (!(x == 0 || x == ~0UL)) {
+		vcpu_printf(vcpu, "%s: %s (%lx) not canonical\n",
+			    __FUNCTION__, name, reg);
+		return 0;
+	}
+#endif
+	return 1;
+}
+
+static int check_selector(struct kvm_vcpu *vcpu, const char *name,
+			  int rpl_ti, int null,
+			  u16 sel)
+{
+	if (rpl_ti && (sel & 7)) {
+		vcpu_printf(vcpu, "%s: %s (%x) nonzero rpl or ti\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	if (null && !sel) {
+		vcpu_printf(vcpu, "%s: %s (%x) zero\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	return 1;
+}
+
+#define MSR_IA32_VMX_CR0_FIXED0 0x486
+#define MSR_IA32_VMX_CR0_FIXED1 0x487
+
+#define MSR_IA32_VMX_CR4_FIXED0 0x488
+#define MSR_IA32_VMX_CR4_FIXED1 0x489
+
+int vm_entry_test_host(struct kvm_vcpu *vcpu)
+{
+	int r = 0;
+	unsigned long cr0 = vmcs_readl(HOST_CR0);
+	unsigned long cr4 = vmcs_readl(HOST_CR4);
+	unsigned long cr3 = vmcs_readl(HOST_CR3);
+	int host_64;
+
+	host_64 = vmcs_read32(VM_EXIT_CONTROLS) & VM_EXIT_HOST_ADD_SPACE_SIZE;
+
+	/* 22.2.2 */
+	r &= check_fixed_bits(vcpu, "host cr0", cr0, MSR_IA32_VMX_CR0_FIXED0,
+			      MSR_IA32_VMX_CR0_FIXED1);
+
+	r &= check_fixed_bits(vcpu, "host cr0", cr4, MSR_IA32_VMX_CR4_FIXED0,
+			      MSR_IA32_VMX_CR4_FIXED1);
+	if ((u64)cr3 >> phys_addr_width()) {
+		vcpu_printf(vcpu, "%s: cr3 (%lx) vs phys addr width\n",
+			    __FUNCTION__, cr3);
+		r = 0;
+	}
+
+	r &= check_canonical(vcpu, "host ia32_sysenter_eip",
+			     vmcs_readl(HOST_IA32_SYSENTER_EIP));
+	r &= check_canonical(vcpu, "host ia32_sysenter_esp",
+			     vmcs_readl(HOST_IA32_SYSENTER_ESP));
+
+	/* 22.2.3 */
+	r &= check_selector(vcpu, "host cs", 1, 1,
+			    vmcs_read16(HOST_CS_SELECTOR));
+	r &= check_selector(vcpu, "host ss", 1, !host_64,
+			    vmcs_read16(HOST_SS_SELECTOR));
+	r &= check_selector(vcpu, "host ds", 1, 0,
+			    vmcs_read16(HOST_DS_SELECTOR));
+	r &= check_selector(vcpu, "host es", 1, 0,
+			    vmcs_read16(HOST_ES_SELECTOR));
+	r &= check_selector(vcpu, "host fs", 1, 0,
+			    vmcs_read16(HOST_FS_SELECTOR));
+	r &= check_selector(vcpu, "host gs", 1, 0,
+			    vmcs_read16(HOST_GS_SELECTOR));
+	r &= check_selector(vcpu, "host tr", 1, 1,
+			    vmcs_read16(HOST_TR_SELECTOR));
+
+#ifdef __x86_64__
+	r &= check_canonical(vcpu, "host fs base",
+			     vmcs_readl(HOST_FS_BASE));
+	r &= check_canonical(vcpu, "host gs base",
+			     vmcs_readl(HOST_GS_BASE));
+	r &= check_canonical(vcpu, "host gdtr base",
+			     vmcs_readl(HOST_GDTR_BASE));
+	r &= check_canonical(vcpu, "host idtr base",
+			     vmcs_readl(HOST_IDTR_BASE));
+#endif
+
+	/* 22.2.4 */
+#ifdef __x86_64__
+	if (!host_64) {
+		vcpu_printf(vcpu, "%s: vm exit controls: !64 bit host\n",
+			    __FUNCTION__);
+		r = 0;
+	}
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 (%lx): !pae\n",
+			    __FUNCTION__, cr4);
+		r = 0;
+	}
+	r &= check_canonical(vcpu, "host rip", vmcs_readl(HOST_RIP));
+#endif
+
+	return r;
+}
+
+int vm_entry_test(struct kvm_vcpu *vcpu)
+{
+	int rg, rh;
+
+	rg = vm_entry_test_guest(vcpu);
+	rh = vm_entry_test_host(vcpu);
+	return rg && rh;
+}
+
+void vmcs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ vmcs_dump ************************\n");
+	vcpu_printf(vcpu, "HOST_CR0 0x%lx\n", vmcs_readl(HOST_CR0));
+	vcpu_printf(vcpu, "HOST_CR3 0x%lx\n", vmcs_readl(HOST_CR3));
+	vcpu_printf(vcpu, "HOST_CR4 0x%lx\n", vmcs_readl(HOST_CR4));
+
+	vcpu_printf(vcpu, "HOST_TR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_TR_BASE 0x%lx\n", vmcs_readl(HOST_TR_BASE));
+
+	vcpu_printf(vcpu, "HOST_GDTR_BASE 0x%lx\n", vmcs_readl(HOST_GDTR_BASE));
+	vcpu_printf(vcpu, "HOST_LDTR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_IDTR_BASE 0x%lx\n", vmcs_readl(HOST_IDTR_BASE));
+
+	vcpu_printf(vcpu, "HOST_CS_SELECTOR 0x%x\n", vmcs_read16(HOST_CS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_DS_SELECTOR 0x%x\n", vmcs_read16(HOST_DS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_ES_SELECTOR 0x%x\n", vmcs_read16(HOST_ES_SELECTOR));
+	vcpu_printf(vcpu, "HOST_FS_SELECTOR 0x%x\n", vmcs_read16(HOST_FS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_GS_SELECTOR 0x%x\n", vmcs_read16(HOST_GS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_SS_SELECTOR 0x%x\n", vmcs_read16(HOST_SS_SELECTOR));
+
+
+	vcpu_printf(vcpu, "VM_ENTRY_CONTROLS 0x%x\n", vmcs_read32(VM_ENTRY_CONTROLS));
+
+	vcpu_printf(vcpu, "GUEST_CR0 0x%lx\n", vmcs_readl(GUEST_CR0));
+	vcpu_printf(vcpu, "GUEST_CR3 0x%lx\n", vmcs_readl(GUEST_CR3));
+	vcpu_printf(vcpu, "GUEST_CR4 0x%lx\n", vmcs_readl(GUEST_CR4));
+
+	vcpu_printf(vcpu, "GUEST_SYSENTER_ESP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_ESP));
+	vcpu_printf(vcpu, "GUEST_SYSENTER_EIP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_EIP));
+
+
+	vcpu_printf(vcpu, "GUEST_IA32_DEBUGCTL 0x%llx\n", vmcs_read64(GUEST_IA32_DEBUGCTL));
+	vcpu_printf(vcpu, "GUEST_DR7 0x%lx\n", vmcs_readl(GUEST_DR7));
+
+	vcpu_printf(vcpu, "GUEST_RFLAGS 0x%lx\n", vmcs_readl(GUEST_RFLAGS));
+	vcpu_printf(vcpu, "GUEST_RIP 0x%lx\n", vmcs_readl(GUEST_RIP));
+
+	vcpu_printf(vcpu, "GUEST_CS_SELECTOR 0x%x\n", vmcs_read16(GUEST_CS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_DS_SELECTOR 0x%x\n", vmcs_read16(GUEST_DS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_ES_SELECTOR 0x%x\n", vmcs_read16(GUEST_ES_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_FS_SELECTOR 0x%x\n", vmcs_read16(GUEST_FS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_GS_SELECTOR 0x%x\n", vmcs_read16(GUEST_GS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_SS_SELECTOR 0x%x\n", vmcs_read16(GUEST_SS_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_TR_SELECTOR 0x%x\n", vmcs_read16(GUEST_TR_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_LDTR_SELECTOR 0x%x\n", vmcs_read16(GUEST_LDTR_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_CS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_CS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_DS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_DS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_ES_AR_BYTES 0x%x\n", vmcs_read32(GUEST_ES_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_FS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_FS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_GS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_GS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_SS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_SS_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_LDTR_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_TR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_TR_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_CS_BASE 0x%lx\n", vmcs_readl(GUEST_CS_BASE));
+	vcpu_printf(vcpu, "GUEST_DS_BASE 0x%lx\n", vmcs_readl(GUEST_DS_BASE));
+	vcpu_printf(vcpu, "GUEST_ES_BASE 0x%lx\n", vmcs_readl(GUEST_ES_BASE));
+	vcpu_printf(vcpu, "GUEST_FS_BASE 0x%lx\n", vmcs_readl(GUEST_FS_BASE));
+	vcpu_printf(vcpu, "GUEST_GS_BASE 0x%lx\n", vmcs_readl(GUEST_GS_BASE));
+	vcpu_printf(vcpu, "GUEST_SS_BASE 0x%lx\n", vmcs_readl(GUEST_SS_BASE));
+
+
+	vcpu_printf(vcpu, "GUEST_LDTR_BASE 0x%lx\n", vmcs_readl(GUEST_LDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_TR_BASE 0x%lx\n", vmcs_readl(GUEST_TR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_CS_LIMIT 0x%x\n", vmcs_read32(GUEST_CS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_DS_LIMIT 0x%x\n", vmcs_read32(GUEST_DS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_ES_LIMIT 0x%x\n", vmcs_read32(GUEST_ES_LIMIT));
+	vcpu_printf(vcpu, "GUEST_FS_LIMIT 0x%x\n", vmcs_read32(GUEST_FS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_GS_LIMIT 0x%x\n", vmcs_read32(GUEST_GS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_SS_LIMIT 0x%x\n", vmcs_read32(GUEST_SS_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_LDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_TR_LIMIT 0x%x\n", vmcs_read32(GUEST_TR_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_BASE 0x%lx\n", vmcs_readl(GUEST_GDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_IDTR_BASE 0x%lx\n", vmcs_readl(GUEST_IDTR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_GDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_IDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_IDTR_LIMIT));
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void regs_dump(struct kvm_vcpu *vcpu)
+{
+	#define REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vcpu->regs[VCPU_REGS_##reg])
+	#define VMCS_REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vmcs_readl(GUEST_##reg))
+
+	vcpu_printf(vcpu, "************************ regs_dump ************************\n");
+	REG_DUMP(RAX);
+	REG_DUMP(RBX);
+	REG_DUMP(RCX);
+	REG_DUMP(RDX);
+	REG_DUMP(RSP);
+	REG_DUMP(RBP);
+	REG_DUMP(RSI);
+	REG_DUMP(RDI);
+	REG_DUMP(R8);
+	REG_DUMP(R9);
+	REG_DUMP(R10);
+	REG_DUMP(R11);
+	REG_DUMP(R12);
+	REG_DUMP(R13);
+	REG_DUMP(R14);
+	REG_DUMP(R15);
+
+	VMCS_REG_DUMP(RSP);
+	VMCS_REG_DUMP(RIP);
+	VMCS_REG_DUMP(RFLAGS);
+
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void sregs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ sregs_dump ************************\n");
+	vcpu_printf(vcpu, "cr0 = 0x%lx\n", guest_cr0());
+	vcpu_printf(vcpu, "cr2 = 0x%lx\n", vcpu->cr2);
+	vcpu_printf(vcpu, "cr3 = 0x%lx\n", vcpu->cr3);
+	vcpu_printf(vcpu, "cr4 = 0x%lx\n", guest_cr4());
+	vcpu_printf(vcpu, "cr8 = 0x%lx\n", vcpu->cr8);
+	vcpu_printf(vcpu, "shadow_efer = 0x%llx\n", vcpu->shadow_efer);
+	vmcs_dump(vcpu);
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+#endif
+
Index: linux-2.6/drivers/kvm/debug.h
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.h
@@ -0,0 +1,21 @@
+#ifndef __KVM_DEBUG_H
+#define __KVM_DEBUG_H
+
+#ifdef KVM_DEBUG
+
+void show_msrs(struct kvm_vcpu *vcpu);
+
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq);
+void show_page(struct kvm_vcpu *vcpu, gva_t addr);
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr);
+void show_code(struct kvm_vcpu *vcpu);
+int vm_entry_test(struct kvm_vcpu *vcpu);
+
+void vmcs_dump(struct kvm_vcpu *vcpu);
+void regs_dump(struct kvm_vcpu *vcpu);
+void sregs_dump(struct kvm_vcpu *vcpu);
+
+#endif
+
+#endif
Index: linux-2.6/drivers/kvm/kvm.h
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm.h
+++ linux-2.6/drivers/kvm/kvm.h
@@ -9,6 +9,8 @@
 
 #include "vmx.h"
 
+#define KVM_DEBUG 1
+
 #define CR0_PE_MASK (1ULL << 0)
 #define CR0_TS_MASK (1ULL << 3)
 #define CR0_NE_MASK (1ULL << 5)
Index: linux-2.6/drivers/kvm/kvm_main.c
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm_main.c
+++ linux-2.6/drivers/kvm/kvm_main.c
@@ -33,6 +33,7 @@
 
 #include "vmx.h"
 #include "x86_emulate.h"
+#include "debug.h"
 
 MODULE_AUTHOR("Qumranet");
 MODULE_LICENSE("GPL");
@@ -1107,6 +1108,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 	int nr_good_msrs;
 
 
+	printk("*** vcpu_setup begin\n");
+	vmcs_dump(vcpu);
+
 	if (!init_rmode_tss(vcpu->kvm)) {
 		ret = 0;
 		goto out;
@@ -1303,6 +1307,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 
 	ret = kvm_mmu_init(vcpu);
 
+	printk("*** vcpu_setup end\n");
+	vmcs_dump(vcpu);
+
 	return ret;
 
 out_free_guest_msrs:
@@ -2618,6 +2625,9 @@ again:
 	fx_save(vcpu->host_fx_image);
 	fx_restore(vcpu->guest_fx_image);
 
+	printk("*** pre launch\n");
+	vmcs_dump(vcpu);
+
 	save_msrs(vcpu->host_msrs, vcpu->nmsrs);
 	load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
 
@@ -2740,6 +2750,9 @@ again:
 		[cr2]"i"(offsetof(struct kvm_vcpu, cr2))
 	      : "cc", "memory" );
 
+	printk("*** post launch\n");
+	vmcs_dump(vcpu);
+
 	++kvm_stat.exits;
 
 	save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);

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_______________________________________________
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1: Type: text/plain, Size: 1817 bytes --]

On Tuesday 07 November 2006 14:25, Avi Kivity wrote:
> Hesse, Christian wrote:
> > On Tuesday 07 November 2006 13:31, Avi Kivity wrote:
> >> Hesse, Christian wrote:
> >>>> Then, please apply the attached patch.  You will need serial console
> >>>> or netconsole, and to
> >>>>
> >>>>    echo 9 > /proc/sysrq-trigger
> >>>>
> >>>> before launching the VM.
> >>>
> >>> There is no patch attached to this mail...
> >>
> >> Sorry, attaching now.
> >
> > There are some undefined values in your code:
> >
> > /usr/src/kvm-module/debug.c: In function 'vmcs_dump':
> > /usr/src/kvm-module/debug.c:924: error: 'HOST_TR_LIMIT' undeclared (first
> > use in this function)
>
> Sorry, refreshed patch attached.

Looks better, but you did not catch them all.

/usr/src/kvm-module/debug.c: In function 'regs_dump':
/usr/src/kvm-module/debug.c:1019: error: 'VCPU_REGS_R8' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1019: error: (Each undeclared identifier is 
reported only once
/usr/src/kvm-module/debug.c:1019: error: for each function it appears in.)
/usr/src/kvm-module/debug.c:1020: error: 'VCPU_REGS_R9' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1021: error: 'VCPU_REGS_R10' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1022: error: 'VCPU_REGS_R11' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1023: error: 'VCPU_REGS_R12' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1024: error: 'VCPU_REGS_R13' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1025: error: 'VCPU_REGS_R14' undeclared (first use 
in this function)
/usr/src/kvm-module/debug.c:1026: error: 'VCPU_REGS_R15' undeclared (first use 
in this function)
-- 
Regards,
Chris

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 373 bytes --]

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_______________________________________________
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 1090 bytes --]

Hesse, Christian wrote:
> On Tuesday 07 November 2006 14:25, Avi Kivity wrote:
>   
>> Hesse, Christian wrote:
>>     
>>> On Tuesday 07 November 2006 13:31, Avi Kivity wrote:
>>>       
>>>> Hesse, Christian wrote:
>>>>         
>>>>>> Then, please apply the attached patch.  You will need serial console
>>>>>> or netconsole, and to
>>>>>>
>>>>>>    echo 9 > /proc/sysrq-trigger
>>>>>>
>>>>>> before launching the VM.
>>>>>>             
>>>>> There is no patch attached to this mail...
>>>>>           
>>>> Sorry, attaching now.
>>>>         
>>> There are some undefined values in your code:
>>>
>>> /usr/src/kvm-module/debug.c: In function 'vmcs_dump':
>>> /usr/src/kvm-module/debug.c:924: error: 'HOST_TR_LIMIT' undeclared (first
>>> use in this function)
>>>       
>> Sorry, refreshed patch attached.
>>     
>
> Looks better, but you did not catch them all.
>
>   

Forgot you're using 32-bit.  #ifdef'ed out.

Is this machine a laptop?  If so, we may be seeing interaction between 
system management mode and VT.

-- 
error compiling committee.c: too many arguments to function


[-- Attachment #2: kvm-debug.patch --]
[-- Type: text/x-patch, Size: 31520 bytes --]

Index: linux-2.6/drivers/kvm/debug.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.c
@@ -0,0 +1,1051 @@
+/*
+ * Kernel-based Virtual Machine driver for Linux
+ *
+ * This module enables machines with Intel VT-x extensions to run virtual
+ * machines without emulation or binary translation.
+ *
+ * Debug support
+ *
+ * Copyright (C) 2006 Qumranet, Inc.
+ *
+ * Authors:
+ *   Yaniv Kamay  <yaniv-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *   Avi Kivity   <avi-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
+ *
+ */
+
+#include <linux/highmem.h>
+
+#include <linux/kvm.h>
+#include "kvm.h"
+#include "debug.h"
+
+#ifdef KVM_DEBUG
+
+static const char *vmx_msr_name[] = {
+	"MSR_EFER", "MSR_STAR", "MSR_CSTAR",
+	"MSR_KERNEL_GS_BASE", "MSR_SYSCALL_MASK", "MSR_LSTAR"
+};
+
+#define NR_VMX_MSR (sizeof(vmx_msr_name) / sizeof(char*))
+
+void show_msrs(struct kvm_vcpu *vcpu)
+{
+	int i;
+
+	for (i = 0; i < NR_VMX_MSR; ++i) {
+		vcpu_printf(vcpu, "%s: %s=0x%llx\n",
+		       __FUNCTION__,
+		       vmx_msr_name[i],
+		       vcpu->guest_msrs[i].data);
+	}
+}
+
+void show_code(struct kvm_vcpu *vcpu)
+{
+	gva_t rip = vmcs_readl(GUEST_RIP);
+	u8 code[50];
+	char buf[30 + 3 * sizeof code];
+	int i;
+
+	if (!is_long_mode())
+		rip += vmcs_readl(GUEST_CS_BASE);
+
+	kvm_read_guest(vcpu, rip, sizeof code, code);
+	for (i = 0; i < sizeof code; ++i)
+		sprintf(buf + i * 3, " %02x", code[i]);
+	vcpu_printf(vcpu, "code: %lx%s\n", rip, buf);
+}
+
+struct gate_struct {
+	u16 offset_low;
+	u16 segment;
+	unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
+	u16 offset_middle;
+	u32 offset_high;
+	u32 zero1;
+} __attribute__((packed));
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq)
+{
+	unsigned long idt_base = vmcs_readl(GUEST_IDTR_BASE);
+	unsigned long idt_limit = vmcs_readl(GUEST_IDTR_LIMIT);
+	struct gate_struct gate;
+
+	if (!is_long_mode())
+		vcpu_printf(vcpu, "%s: not in long mode\n", __FUNCTION__);
+
+	if (!is_long_mode() || idt_limit < irq * sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+
+	if (kvm_read_guest(vcpu, idt_base + irq * sizeof(gate), sizeof(gate), &gate) != sizeof(gate)) {
+		vcpu_printf(vcpu, "%s: 0x%x read_guest err\n",
+			   __FUNCTION__,
+			   irq);
+		return;
+	}
+	vcpu_printf(vcpu, "%s: 0x%x handler 0x%llx\n",
+		   __FUNCTION__,
+		   irq,
+		   ((u64)gate.offset_high << 32) |
+		   ((u64)gate.offset_middle << 16) |
+		   gate.offset_low);
+}
+
+void show_page(struct kvm_vcpu *vcpu,
+			     gva_t addr)
+{
+	u64 *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	if (!buf)
+		return;
+
+	addr &= PAGE_MASK;
+	if (kvm_read_guest(vcpu, addr, PAGE_SIZE, buf)) {
+		int i;
+		for (i = 0; i <  PAGE_SIZE / sizeof(u64) ; i++) {
+			u8 *ptr = (u8*)&buf[i];
+			int j;
+			vcpu_printf(vcpu, " 0x%16.16lx:",
+				   addr + i * sizeof(u64));
+			for (j = 0; j < sizeof(u64) ; j++)
+				vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+			vcpu_printf(vcpu, "\n");
+		}
+	}
+	kfree(buf);
+}
+
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr)
+{
+	u64 buf;
+
+	if (kvm_read_guest(vcpu, addr, sizeof(u64), &buf) == sizeof(u64)) {
+		u8 *ptr = (u8*)&buf;
+		int j;
+		vcpu_printf(vcpu, " 0x%16.16lx:", addr);
+		for (j = 0; j < sizeof(u64) ; j++)
+			vcpu_printf(vcpu, " 0x%2.2x", ptr[j]);
+		vcpu_printf(vcpu, "\n");
+	}
+}
+
+#define IA32_DEBUGCTL_RESERVED_BITS 0xfffffffffffffe3cULL
+
+static int is_canonical(unsigned long addr)
+{
+       return  addr == ((long)addr << 16) >> 16;
+}
+
+int vm_entry_test_guest(struct kvm_vcpu *vcpu)
+{
+	unsigned long cr0;
+	unsigned long cr4;
+	unsigned long cr3;
+	unsigned long dr7;
+	u64 ia32_debugctl;
+	unsigned long sysenter_esp;
+	unsigned long sysenter_eip;
+	unsigned long rflags;
+
+	int long_mode;
+	int virtual8086;
+
+	#define RFLAGS_VM (1 << 17)
+	#define RFLAGS_RF (1 << 9)
+
+
+	#define VIR8086_SEG_BASE_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_BASE) != \
+		    (unsigned long)vmcs_read16(GUEST_##seg##_SELECTOR) << 4) {\
+			vcpu_printf(vcpu, "%s: "#seg" base 0x%lx in "\
+				   "virtual8086 is not "#seg" selector 0x%x"\
+				   " shifted right 4 bits\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE),\
+			   vmcs_read16(GUEST_##seg##_SELECTOR));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_LIMIT_TEST(seg)\
+		if (vmcs_readl(GUEST_##seg##_LIMIT) != 0x0ffff) { \
+			vcpu_printf(vcpu, "%s: "#seg" limit 0x%lx in "\
+				   "virtual8086 is not 0xffff\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_LIMIT));\
+			return 0;\
+		}
+
+	#define VIR8086_SEG_AR_TEST(seg)\
+		if (vmcs_read32(GUEST_##seg##_AR_BYTES) != 0x0f3) { \
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x in "\
+				   "virtual8086 is not 0xf3\n",\
+			   __FUNCTION__,\
+			   vmcs_read32(GUEST_##seg##_AR_BYTES));\
+			return 0;\
+		}
+
+
+	cr0 = vmcs_readl(GUEST_CR0);
+
+	if (!(cr0 & CR0_PG_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PG is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_PE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, PE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_NE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, NE is not set\n",
+			   __FUNCTION__, cr0);
+		return 0;
+	}
+
+	if (!(cr0 & CR0_WP_MASK)) {
+		vcpu_printf(vcpu, "%s: cr0 0x%lx, WP is not set\n",
+			   __FUNCTION__, cr0);
+	}
+
+	cr4 = vmcs_readl(GUEST_CR4);
+
+	if (!(cr4 & CR4_VMXE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, VMXE is not set\n",
+			   __FUNCTION__, cr4);
+		return 0;
+	}
+
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 0x%lx, PAE is not set\n",
+			   __FUNCTION__, cr4);
+	}
+
+	ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
+
+	if (ia32_debugctl & IA32_DEBUGCTL_RESERVED_BITS ) {
+		vcpu_printf(vcpu, "%s: ia32_debugctl 0x%llx, reserve bits\n",
+			   __FUNCTION__, ia32_debugctl);
+		return 0;
+	}
+
+	long_mode = is_long_mode();
+
+	if (long_mode) {
+	}
+
+	if ( long_mode && !(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: long mode and not PAE\n",
+			   __FUNCTION__);
+		return 0;
+	}
+
+	cr3 = vmcs_readl(GUEST_CR3);
+
+	if (cr3 & CR3_L_MODE_RESEVED_BITS) {
+		vcpu_printf(vcpu, "%s: cr3 0x%lx, reserved bits\n",
+			   __FUNCTION__, cr3);
+		return 0;
+	}
+
+	if ( !long_mode && (cr4 & CR4_PAE_MASK)) {
+		/* check the 4 PDPTEs for reserved bits */
+		unsigned long pdpt_pfn = cr3 >> PAGE_SHIFT;
+		int i;
+		u64 pdpte;
+		unsigned offset = (cr3 & (PAGE_SIZE-1)) >> 5;
+		u64 *pdpt = kmap_atomic(pfn_to_page(pdpt_pfn), KM_USER0);
+
+		for (i = 0; i < 4; ++i) {
+			pdpte = pdpt[offset + i];
+			if ((pdpte & 1) && (pdpte & 0xfffffff0000001e6ull))
+				break;
+		}
+
+		kunmap_atomic(pdpt, KM_USER0);
+
+		if (i != 4) {
+			vcpu_printf(vcpu, "%s: pae cr3[%d] 0x%llx, reserved bits\n",
+				   __FUNCTION__, i, pdpte);
+			return 0;
+		}
+	}
+
+	dr7 = vmcs_readl(GUEST_DR7);
+
+	if (dr7 & ~((1ULL << 32) - 1)) {
+		vcpu_printf(vcpu, "%s: dr7 0x%lx, reserved bits\n",
+			   __FUNCTION__, dr7);
+		return 0;
+	}
+
+	sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
+
+	if (!is_canonical(sysenter_esp)) {
+		vcpu_printf(vcpu, "%s: sysenter_esp 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_esp);
+		return 0;
+	}
+
+	sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
+
+	if (!is_canonical(sysenter_eip)) {
+		vcpu_printf(vcpu, "%s: sysenter_eip 0x%lx, not canonical\n",
+			   __FUNCTION__, sysenter_eip);
+		return 0;
+	}
+
+	rflags = vmcs_readl(GUEST_RFLAGS);
+	virtual8086 = rflags & RFLAGS_VM;
+
+
+	if (vmcs_read16(GUEST_TR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: tr selctor 0x%x, TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_TR_SELECTOR));
+	       return 0;
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	      vmcs_read16(GUEST_LDTR_SELECTOR) & SELECTOR_TI_MASK) {
+	       vcpu_printf(vcpu, "%s: ldtr selctor 0x%x,"
+				     " is usable and TI is set\n",
+			   __FUNCTION__, vmcs_read16(GUEST_LDTR_SELECTOR));
+	       return 0;
+	}
+
+	if (!virtual8086 &&
+	    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) !=
+	    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK)) {
+		vcpu_printf(vcpu, "%s: ss selctor 0x%x cs selctor 0x%x,"
+				     " not same RPL\n",
+			   __FUNCTION__,
+			   vmcs_read16(GUEST_SS_SELECTOR),
+			   vmcs_read16(GUEST_CS_SELECTOR));
+		return 0;
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_BASE_TEST(CS);
+		VIR8086_SEG_BASE_TEST(SS);
+		VIR8086_SEG_BASE_TEST(DS);
+		VIR8086_SEG_BASE_TEST(ES);
+		VIR8086_SEG_BASE_TEST(FS);
+		VIR8086_SEG_BASE_TEST(GS);
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_TR_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_FS_BASE)) ||
+	    !is_canonical(vmcs_readl(GUEST_GS_BASE)) ) {
+		vcpu_printf(vcpu, "%s: TR 0x%lx FS 0x%lx or GS 0x%lx base"
+				      " is not canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_TR_BASE),
+			   vmcs_readl(GUEST_FS_BASE),
+			   vmcs_readl(GUEST_GS_BASE));
+		return 0;
+
+	}
+
+	if (!(vmcs_read32(GUEST_LDTR_AR_BYTES) & AR_UNUSABLE_MASK) &&
+	    !is_canonical(vmcs_readl(GUEST_LDTR_BASE))) {
+		vcpu_printf(vcpu, "%s: LDTR base 0x%lx, usable and is not"
+				      " canonical\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_LDTR_BASE));
+		return 0;
+	}
+
+	if ((vmcs_readl(GUEST_CS_BASE) & ~((1ULL << 32) - 1))) {
+		vcpu_printf(vcpu, "%s: CS base 0x%lx, not all bits 63-32"
+				      " are zero\n",
+			   __FUNCTION__,
+			   vmcs_readl(GUEST_CS_BASE));
+		return 0;
+	}
+
+	#define SEG_BASE_TEST(seg)\
+	if ( !(vmcs_read32(GUEST_##seg##_AR_BYTES) & AR_UNUSABLE_MASK) &&\
+	     (vmcs_readl(GUEST_##seg##_BASE) & ~((1ULL << 32) - 1))) {\
+		vcpu_printf(vcpu, "%s: "#seg" base 0x%lx, is usable and not"\
+						" all bits 63-32 are zero\n",\
+			   __FUNCTION__,\
+			   vmcs_readl(GUEST_##seg##_BASE));\
+		return 0;\
+	}
+	SEG_BASE_TEST(SS);
+	SEG_BASE_TEST(DS);
+	SEG_BASE_TEST(ES);
+
+	if (virtual8086) {
+		VIR8086_SEG_LIMIT_TEST(CS);
+		VIR8086_SEG_LIMIT_TEST(SS);
+		VIR8086_SEG_LIMIT_TEST(DS);
+		VIR8086_SEG_LIMIT_TEST(ES);
+		VIR8086_SEG_LIMIT_TEST(FS);
+		VIR8086_SEG_LIMIT_TEST(GS);
+	}
+
+	if (virtual8086) {
+		VIR8086_SEG_AR_TEST(CS);
+		VIR8086_SEG_AR_TEST(SS);
+		VIR8086_SEG_AR_TEST(DS);
+		VIR8086_SEG_AR_TEST(ES);
+		VIR8086_SEG_AR_TEST(FS);
+		VIR8086_SEG_AR_TEST(GS);
+	} else {
+
+		u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
+		u32 ss_ar = vmcs_read32(GUEST_SS_AR_BYTES);
+		u32 tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
+		u32 ldtr_ar = vmcs_read32(GUEST_LDTR_AR_BYTES);
+
+		#define SEG_G_TEST(seg) {					\
+		u32 lim = vmcs_read32(GUEST_##seg##_LIMIT);		\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);		\
+		int err = 0;							\
+		if (((lim & ~PAGE_MASK) != ~PAGE_MASK) && (ar & AR_G_MASK))	\
+			err = 1;						\
+		if ((lim & ~((1u << 20) - 1)) && !(ar & AR_G_MASK))		\
+			err = 1;						\
+		if (err) {							\
+			vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, G err. lim"	\
+							" is 0x%x\n",		\
+						   __FUNCTION__,		\
+						   ar, lim);			\
+			return 0;						\
+		}								\
+		}
+
+
+		if (!(cs_ar & AR_TYPE_ACCESSES_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, accesses is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_TYPE_CODE_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, code is clear\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, type is sys\n",
+			   __FUNCTION__,
+			   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 8 && (cs_ar & AR_TYPE_MASK) < 12 &&
+		    AR_DPL(cs_ar) !=
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if ((cs_ar & AR_TYPE_MASK) >= 13 && (cs_ar & AR_TYPE_MASK) < 16 &&
+		    AR_DPL(cs_ar) >
+		    (vmcs_read16(GUEST_CS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: cs AR 0x%x, "
+					      "DPL greater than RPL\n",
+				   __FUNCTION__,
+				   cs_ar);
+			return 0;
+		}
+
+		if (!(cs_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, not "
+						      "present\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if ((cs_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: CS AR 0x%x, reseved"
+						      " bits are set\n",
+					   __FUNCTION__,
+					   cs_ar);
+				return 0;
+		}
+
+		if (long_mode & (cs_ar & AR_L_MASK) && (cs_ar & AR_DB_MASK)) {
+			vcpu_printf(vcpu, "%s: CS AR 0x%x, DB and L are set"
+					      " in long mode\n",
+					   __FUNCTION__,
+					   cs_ar);
+			return 0;
+
+		}
+
+		SEG_G_TEST(CS);
+
+		if (!(ss_ar & AR_UNUSABLE_MASK)) {
+		    if ((ss_ar & AR_TYPE_MASK) != 3 &&
+			(ss_ar & AR_TYPE_MASK) != 7 ) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and type"
+					      " is not 3 or 7\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+
+		    if (!(ss_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: ss AR 0x%x, usable and"
+					      " is sys\n",
+			   __FUNCTION__,
+			   ss_ar);
+			return 0;
+		    }
+		    if (!(ss_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: SS AR 0x%x, usable"
+						      " and  not present\n",
+					   __FUNCTION__,
+					   ss_ar);
+				return 0;
+		    }
+
+		    if ((ss_ar & AR_RESERVD_MASK)) {
+					vcpu_printf(vcpu, "%s: SS AR 0x%x, reseved"
+							      " bits are set\n",
+						   __FUNCTION__,
+						   ss_ar);
+					return 0;
+		    }
+
+		    SEG_G_TEST(SS);
+
+		}
+
+		if (AR_DPL(ss_ar) !=
+		    (vmcs_read16(GUEST_SS_SELECTOR) & SELECTOR_RPL_MASK) ) {
+			vcpu_printf(vcpu, "%s: SS AR 0x%x, "
+					      "DPL not as RPL\n",
+				   __FUNCTION__,
+				   ss_ar);
+			return 0;
+		}
+
+		#define SEG_AR_TEST(seg) {\
+		u32 ar = vmcs_read32(GUEST_##seg##_AR_BYTES);\
+		if (!(ar & AR_UNUSABLE_MASK)) {\
+			if (!(ar & AR_TYPE_ACCESSES_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"usable and not accesses\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_CODE_MASK) &&\
+			    !(ar & AR_TYPE_READABLE_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+						"code and not readable\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if (!(ar & AR_S_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " is sys\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_TYPE_MASK) >= 0 && \
+			    (ar & AR_TYPE_MASK) < 12 && \
+			    AR_DPL(ar) < (vmcs_read16(GUEST_##seg##_SELECTOR) & \
+					  SELECTOR_RPL_MASK) ) {\
+				    vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, "\
+					      "DPL less than RPL\n",\
+					       __FUNCTION__,\
+					       ar);\
+				    return 0;\
+			}\
+			if (!(ar & AR_P_MASK)) {\
+				vcpu_printf(vcpu, "%s: "#seg" AR 0x%x, usable and"\
+					      " not present\n",\
+					   __FUNCTION__,\
+					   ar);\
+				return 0;\
+			}\
+			if ((ar & AR_RESERVD_MASK)) {\
+					vcpu_printf(vcpu, "%s: "#seg" AR"\
+							" 0x%x, reseved"\
+							" bits are set\n",\
+						   __FUNCTION__,\
+						   ar);\
+					return 0;\
+			}\
+			SEG_G_TEST(seg)\
+		}\
+		}
+
+#undef DS
+#undef ES
+#undef FS
+#undef GS
+
+		SEG_AR_TEST(DS);
+		SEG_AR_TEST(ES);
+		SEG_AR_TEST(FS);
+		SEG_AR_TEST(GS);
+
+		// TR test
+		if (long_mode) {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, long"
+						      " mode and not 64bit busy"
+						      " tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+		} else {
+			if ((tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_32_TSS &&
+			    (tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_16_TSS) {
+				vcpu_printf(vcpu, "%s: TR AR 0x%x, legacy"
+						      " mode and not 16/32bit "
+						      "busy tss\n",
+				   __FUNCTION__,
+				   tr_ar);
+				return 0;
+			}
+
+		}
+		if ((tr_ar & AR_S_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, S is set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		if (!(tr_ar & AR_P_MASK)) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, P is not set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+
+		if ((tr_ar & (AR_RESERVD_MASK| AR_UNUSABLE_MASK))) {
+			vcpu_printf(vcpu, "%s: TR AR 0x%x, reserved bit are"
+					      " set\n",
+				   __FUNCTION__,
+				   tr_ar);
+			return 0;
+		}
+		SEG_G_TEST(TR);
+
+		// TR test
+		if (!(ldtr_ar & AR_UNUSABLE_MASK)) {
+
+			if ((ldtr_ar & AR_TYPE_MASK) != AR_TYPE_LDT) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " bad type\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+			    return 0;
+			}
+
+			if ((ldtr_ar & AR_S_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " S is set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+
+			if (!(ldtr_ar & AR_P_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " P is not set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			if ((ldtr_ar & AR_RESERVD_MASK)) {
+				vcpu_printf(vcpu, "%s: LDTR AR 0x%x,"
+						      " reserved bit are  set\n",
+					   __FUNCTION__,
+					   ldtr_ar);
+				return 0;
+			}
+			SEG_G_TEST(LDTR);
+		}
+	}
+
+	// GDTR and IDTR
+
+
+	#define IDT_GDT_TEST(reg)\
+	if (!is_canonical(vmcs_readl(GUEST_##reg##_BASE))) {\
+		vcpu_printf(vcpu, "%s: "#reg" BASE 0x%lx, not canonical\n",\
+					   __FUNCTION__,\
+					   vmcs_readl(GUEST_##reg##_BASE));\
+		return 0;\
+	}\
+	if (vmcs_read32(GUEST_##reg##_LIMIT) >> 16) {\
+		vcpu_printf(vcpu, "%s: "#reg" LIMIT 0x%x, size err\n",\
+				   __FUNCTION__,\
+				   vmcs_read32(GUEST_##reg##_LIMIT));\
+		return 0;\
+	}\
+
+	IDT_GDT_TEST(GDTR);
+	IDT_GDT_TEST(IDTR);
+
+
+	// RIP
+
+	if ((!long_mode || !(vmcs_read32(GUEST_CS_AR_BYTES) & AR_L_MASK)) &&
+	    vmcs_readl(GUEST_RIP) & ~((1ULL << 32) - 1) ){
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, size err\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	if (!is_canonical(vmcs_readl(GUEST_RIP))) {
+		vcpu_printf(vcpu, "%s: RIP 0x%lx, not canonical\n",
+				   __FUNCTION__,
+				   vmcs_readl(GUEST_RIP));
+		return 0;
+	}
+
+	// RFLAGS
+	#define RFLAGS_RESEVED_CLEAR_BITS\
+		(~((1ULL << 22) - 1) | (1ULL << 15) | (1ULL << 5) | (1ULL << 3))
+	#define RFLAGS_RESEVED_SET_BITS (1 << 1)
+
+	if ((rflags & RFLAGS_RESEVED_CLEAR_BITS) ||
+	    !(rflags & RFLAGS_RESEVED_SET_BITS)) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, reserved bits 0x%llx 0x%x\n",
+			   __FUNCTION__,
+			   rflags,
+			   RFLAGS_RESEVED_CLEAR_BITS,
+			   RFLAGS_RESEVED_SET_BITS);
+		return 0;
+	}
+
+	if (long_mode && virtual8086) {
+		vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, vm and long mode\n",
+				   __FUNCTION__,
+				   rflags);
+		return 0;
+	}
+
+
+	if (!(rflags & RFLAGS_RF)) {
+		u32 vm_entry_info = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
+		if ((vm_entry_info & INTR_INFO_VALID_MASK) &&
+		    (vm_entry_info & INTR_INFO_INTR_TYPE_MASK) ==
+		    INTR_TYPE_EXT_INTR) {
+			vcpu_printf(vcpu, "%s: RFLAGS 0x%lx, external"
+					      " interrupt and RF is clear\n",
+				   __FUNCTION__,
+				   rflags);
+			return 0;
+		}
+
+	}
+
+	// to be continued from Checks on Guest Non-Register State (22.3.1.5)
+	return 1;
+}
+
+static int check_fixed_bits(struct kvm_vcpu *vcpu, const char *reg,
+			    unsigned long cr,
+			    u32 msr_fixed_0, u32 msr_fixed_1)
+{
+	u64 fixed_bits_0, fixed_bits_1;
+
+	rdmsrl(msr_fixed_0, fixed_bits_0);
+	rdmsrl(msr_fixed_1, fixed_bits_1);
+	if ((cr & fixed_bits_0) != fixed_bits_0) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx unset\n",
+			   __FUNCTION__, reg, cr, fixed_bits_0);
+		return 0;
+	}
+	if ((~cr & ~fixed_bits_1) != ~fixed_bits_1) {
+		vcpu_printf(vcpu, "%s: %s (%lx) has one of %llx set\n",
+			   __FUNCTION__, reg, cr, ~fixed_bits_1);
+		return 0;
+	}
+	return 1;
+}
+
+static int phys_addr_width(void)
+{
+	unsigned eax, ebx, ecx, edx;
+
+	cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+	return eax & 0xff;
+}
+
+static int check_canonical(struct kvm_vcpu *vcpu, const char *name,
+			   unsigned long reg)
+{
+#ifdef __x86_64__
+	unsigned long x;
+
+	if (sizeof(reg) == 4)
+		return 1;
+	x = (long)reg >> 48;
+	if (!(x == 0 || x == ~0UL)) {
+		vcpu_printf(vcpu, "%s: %s (%lx) not canonical\n",
+			    __FUNCTION__, name, reg);
+		return 0;
+	}
+#endif
+	return 1;
+}
+
+static int check_selector(struct kvm_vcpu *vcpu, const char *name,
+			  int rpl_ti, int null,
+			  u16 sel)
+{
+	if (rpl_ti && (sel & 7)) {
+		vcpu_printf(vcpu, "%s: %s (%x) nonzero rpl or ti\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	if (null && !sel) {
+		vcpu_printf(vcpu, "%s: %s (%x) zero\n",
+			    __FUNCTION__, name, sel);
+		return 0;
+	}
+	return 1;
+}
+
+#define MSR_IA32_VMX_CR0_FIXED0 0x486
+#define MSR_IA32_VMX_CR0_FIXED1 0x487
+
+#define MSR_IA32_VMX_CR4_FIXED0 0x488
+#define MSR_IA32_VMX_CR4_FIXED1 0x489
+
+int vm_entry_test_host(struct kvm_vcpu *vcpu)
+{
+	int r = 0;
+	unsigned long cr0 = vmcs_readl(HOST_CR0);
+	unsigned long cr4 = vmcs_readl(HOST_CR4);
+	unsigned long cr3 = vmcs_readl(HOST_CR3);
+	int host_64;
+
+	host_64 = vmcs_read32(VM_EXIT_CONTROLS) & VM_EXIT_HOST_ADD_SPACE_SIZE;
+
+	/* 22.2.2 */
+	r &= check_fixed_bits(vcpu, "host cr0", cr0, MSR_IA32_VMX_CR0_FIXED0,
+			      MSR_IA32_VMX_CR0_FIXED1);
+
+	r &= check_fixed_bits(vcpu, "host cr0", cr4, MSR_IA32_VMX_CR4_FIXED0,
+			      MSR_IA32_VMX_CR4_FIXED1);
+	if ((u64)cr3 >> phys_addr_width()) {
+		vcpu_printf(vcpu, "%s: cr3 (%lx) vs phys addr width\n",
+			    __FUNCTION__, cr3);
+		r = 0;
+	}
+
+	r &= check_canonical(vcpu, "host ia32_sysenter_eip",
+			     vmcs_readl(HOST_IA32_SYSENTER_EIP));
+	r &= check_canonical(vcpu, "host ia32_sysenter_esp",
+			     vmcs_readl(HOST_IA32_SYSENTER_ESP));
+
+	/* 22.2.3 */
+	r &= check_selector(vcpu, "host cs", 1, 1,
+			    vmcs_read16(HOST_CS_SELECTOR));
+	r &= check_selector(vcpu, "host ss", 1, !host_64,
+			    vmcs_read16(HOST_SS_SELECTOR));
+	r &= check_selector(vcpu, "host ds", 1, 0,
+			    vmcs_read16(HOST_DS_SELECTOR));
+	r &= check_selector(vcpu, "host es", 1, 0,
+			    vmcs_read16(HOST_ES_SELECTOR));
+	r &= check_selector(vcpu, "host fs", 1, 0,
+			    vmcs_read16(HOST_FS_SELECTOR));
+	r &= check_selector(vcpu, "host gs", 1, 0,
+			    vmcs_read16(HOST_GS_SELECTOR));
+	r &= check_selector(vcpu, "host tr", 1, 1,
+			    vmcs_read16(HOST_TR_SELECTOR));
+
+#ifdef __x86_64__
+	r &= check_canonical(vcpu, "host fs base",
+			     vmcs_readl(HOST_FS_BASE));
+	r &= check_canonical(vcpu, "host gs base",
+			     vmcs_readl(HOST_GS_BASE));
+	r &= check_canonical(vcpu, "host gdtr base",
+			     vmcs_readl(HOST_GDTR_BASE));
+	r &= check_canonical(vcpu, "host idtr base",
+			     vmcs_readl(HOST_IDTR_BASE));
+#endif
+
+	/* 22.2.4 */
+#ifdef __x86_64__
+	if (!host_64) {
+		vcpu_printf(vcpu, "%s: vm exit controls: !64 bit host\n",
+			    __FUNCTION__);
+		r = 0;
+	}
+	if (!(cr4 & CR4_PAE_MASK)) {
+		vcpu_printf(vcpu, "%s: cr4 (%lx): !pae\n",
+			    __FUNCTION__, cr4);
+		r = 0;
+	}
+	r &= check_canonical(vcpu, "host rip", vmcs_readl(HOST_RIP));
+#endif
+
+	return r;
+}
+
+int vm_entry_test(struct kvm_vcpu *vcpu)
+{
+	int rg, rh;
+
+	rg = vm_entry_test_guest(vcpu);
+	rh = vm_entry_test_host(vcpu);
+	return rg && rh;
+}
+
+void vmcs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ vmcs_dump ************************\n");
+	vcpu_printf(vcpu, "HOST_CR0 0x%lx\n", vmcs_readl(HOST_CR0));
+	vcpu_printf(vcpu, "HOST_CR3 0x%lx\n", vmcs_readl(HOST_CR3));
+	vcpu_printf(vcpu, "HOST_CR4 0x%lx\n", vmcs_readl(HOST_CR4));
+
+	vcpu_printf(vcpu, "HOST_TR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_TR_BASE 0x%lx\n", vmcs_readl(HOST_TR_BASE));
+
+	vcpu_printf(vcpu, "HOST_GDTR_BASE 0x%lx\n", vmcs_readl(HOST_GDTR_BASE));
+	vcpu_printf(vcpu, "HOST_LDTR_SELECTOR 0x%x\n", vmcs_read16(HOST_TR_SELECTOR));
+	vcpu_printf(vcpu, "HOST_IDTR_BASE 0x%lx\n", vmcs_readl(HOST_IDTR_BASE));
+
+	vcpu_printf(vcpu, "HOST_CS_SELECTOR 0x%x\n", vmcs_read16(HOST_CS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_DS_SELECTOR 0x%x\n", vmcs_read16(HOST_DS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_ES_SELECTOR 0x%x\n", vmcs_read16(HOST_ES_SELECTOR));
+	vcpu_printf(vcpu, "HOST_FS_SELECTOR 0x%x\n", vmcs_read16(HOST_FS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_GS_SELECTOR 0x%x\n", vmcs_read16(HOST_GS_SELECTOR));
+	vcpu_printf(vcpu, "HOST_SS_SELECTOR 0x%x\n", vmcs_read16(HOST_SS_SELECTOR));
+
+
+	vcpu_printf(vcpu, "VM_ENTRY_CONTROLS 0x%x\n", vmcs_read32(VM_ENTRY_CONTROLS));
+
+	vcpu_printf(vcpu, "GUEST_CR0 0x%lx\n", vmcs_readl(GUEST_CR0));
+	vcpu_printf(vcpu, "GUEST_CR3 0x%lx\n", vmcs_readl(GUEST_CR3));
+	vcpu_printf(vcpu, "GUEST_CR4 0x%lx\n", vmcs_readl(GUEST_CR4));
+
+	vcpu_printf(vcpu, "GUEST_SYSENTER_ESP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_ESP));
+	vcpu_printf(vcpu, "GUEST_SYSENTER_EIP 0x%lx\n", vmcs_readl(GUEST_SYSENTER_EIP));
+
+
+	vcpu_printf(vcpu, "GUEST_IA32_DEBUGCTL 0x%llx\n", vmcs_read64(GUEST_IA32_DEBUGCTL));
+	vcpu_printf(vcpu, "GUEST_DR7 0x%lx\n", vmcs_readl(GUEST_DR7));
+
+	vcpu_printf(vcpu, "GUEST_RFLAGS 0x%lx\n", vmcs_readl(GUEST_RFLAGS));
+	vcpu_printf(vcpu, "GUEST_RIP 0x%lx\n", vmcs_readl(GUEST_RIP));
+
+	vcpu_printf(vcpu, "GUEST_CS_SELECTOR 0x%x\n", vmcs_read16(GUEST_CS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_DS_SELECTOR 0x%x\n", vmcs_read16(GUEST_DS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_ES_SELECTOR 0x%x\n", vmcs_read16(GUEST_ES_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_FS_SELECTOR 0x%x\n", vmcs_read16(GUEST_FS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_GS_SELECTOR 0x%x\n", vmcs_read16(GUEST_GS_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_SS_SELECTOR 0x%x\n", vmcs_read16(GUEST_SS_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_TR_SELECTOR 0x%x\n", vmcs_read16(GUEST_TR_SELECTOR));
+	vcpu_printf(vcpu, "GUEST_LDTR_SELECTOR 0x%x\n", vmcs_read16(GUEST_LDTR_SELECTOR));
+
+	vcpu_printf(vcpu, "GUEST_CS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_CS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_DS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_DS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_ES_AR_BYTES 0x%x\n", vmcs_read32(GUEST_ES_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_FS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_FS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_GS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_GS_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_SS_AR_BYTES 0x%x\n", vmcs_read32(GUEST_SS_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_LDTR_AR_BYTES));
+	vcpu_printf(vcpu, "GUEST_TR_AR_BYTES 0x%x\n", vmcs_read32(GUEST_TR_AR_BYTES));
+
+	vcpu_printf(vcpu, "GUEST_CS_BASE 0x%lx\n", vmcs_readl(GUEST_CS_BASE));
+	vcpu_printf(vcpu, "GUEST_DS_BASE 0x%lx\n", vmcs_readl(GUEST_DS_BASE));
+	vcpu_printf(vcpu, "GUEST_ES_BASE 0x%lx\n", vmcs_readl(GUEST_ES_BASE));
+	vcpu_printf(vcpu, "GUEST_FS_BASE 0x%lx\n", vmcs_readl(GUEST_FS_BASE));
+	vcpu_printf(vcpu, "GUEST_GS_BASE 0x%lx\n", vmcs_readl(GUEST_GS_BASE));
+	vcpu_printf(vcpu, "GUEST_SS_BASE 0x%lx\n", vmcs_readl(GUEST_SS_BASE));
+
+
+	vcpu_printf(vcpu, "GUEST_LDTR_BASE 0x%lx\n", vmcs_readl(GUEST_LDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_TR_BASE 0x%lx\n", vmcs_readl(GUEST_TR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_CS_LIMIT 0x%x\n", vmcs_read32(GUEST_CS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_DS_LIMIT 0x%x\n", vmcs_read32(GUEST_DS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_ES_LIMIT 0x%x\n", vmcs_read32(GUEST_ES_LIMIT));
+	vcpu_printf(vcpu, "GUEST_FS_LIMIT 0x%x\n", vmcs_read32(GUEST_FS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_GS_LIMIT 0x%x\n", vmcs_read32(GUEST_GS_LIMIT));
+	vcpu_printf(vcpu, "GUEST_SS_LIMIT 0x%x\n", vmcs_read32(GUEST_SS_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_LDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_LDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_TR_LIMIT 0x%x\n", vmcs_read32(GUEST_TR_LIMIT));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_BASE 0x%lx\n", vmcs_readl(GUEST_GDTR_BASE));
+	vcpu_printf(vcpu, "GUEST_IDTR_BASE 0x%lx\n", vmcs_readl(GUEST_IDTR_BASE));
+
+	vcpu_printf(vcpu, "GUEST_GDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_GDTR_LIMIT));
+	vcpu_printf(vcpu, "GUEST_IDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_IDTR_LIMIT));
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void regs_dump(struct kvm_vcpu *vcpu)
+{
+	#define REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vcpu->regs[VCPU_REGS_##reg])
+	#define VMCS_REG_DUMP(reg) \
+		vcpu_printf(vcpu, #reg" = 0x%lx\n", vmcs_readl(GUEST_##reg))
+
+	vcpu_printf(vcpu, "************************ regs_dump ************************\n");
+	REG_DUMP(RAX);
+	REG_DUMP(RBX);
+	REG_DUMP(RCX);
+	REG_DUMP(RDX);
+	REG_DUMP(RSP);
+	REG_DUMP(RBP);
+	REG_DUMP(RSI);
+	REG_DUMP(RDI);
+#ifdef __x86_64__
+	REG_DUMP(R8);
+	REG_DUMP(R9);
+	REG_DUMP(R10);
+	REG_DUMP(R11);
+	REG_DUMP(R12);
+	REG_DUMP(R13);
+	REG_DUMP(R14);
+	REG_DUMP(R15);
+#endif
+
+	VMCS_REG_DUMP(RSP);
+	VMCS_REG_DUMP(RIP);
+	VMCS_REG_DUMP(RFLAGS);
+
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+void sregs_dump(struct kvm_vcpu *vcpu)
+{
+	vcpu_printf(vcpu, "************************ sregs_dump ************************\n");
+	vcpu_printf(vcpu, "cr0 = 0x%lx\n", guest_cr0());
+	vcpu_printf(vcpu, "cr2 = 0x%lx\n", vcpu->cr2);
+	vcpu_printf(vcpu, "cr3 = 0x%lx\n", vcpu->cr3);
+	vcpu_printf(vcpu, "cr4 = 0x%lx\n", guest_cr4());
+	vcpu_printf(vcpu, "cr8 = 0x%lx\n", vcpu->cr8);
+	vcpu_printf(vcpu, "shadow_efer = 0x%llx\n", vcpu->shadow_efer);
+	vmcs_dump(vcpu);
+	vcpu_printf(vcpu, "***********************************************************\n");
+}
+
+#endif
+
Index: linux-2.6/drivers/kvm/debug.h
===================================================================
--- /dev/null
+++ linux-2.6/drivers/kvm/debug.h
@@ -0,0 +1,21 @@
+#ifndef __KVM_DEBUG_H
+#define __KVM_DEBUG_H
+
+#ifdef KVM_DEBUG
+
+void show_msrs(struct kvm_vcpu *vcpu);
+
+
+void show_irq(struct kvm_vcpu *vcpu,  int irq);
+void show_page(struct kvm_vcpu *vcpu, gva_t addr);
+void show_u64(struct kvm_vcpu *vcpu, gva_t addr);
+void show_code(struct kvm_vcpu *vcpu);
+int vm_entry_test(struct kvm_vcpu *vcpu);
+
+void vmcs_dump(struct kvm_vcpu *vcpu);
+void regs_dump(struct kvm_vcpu *vcpu);
+void sregs_dump(struct kvm_vcpu *vcpu);
+
+#endif
+
+#endif
Index: linux-2.6/drivers/kvm/kvm.h
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm.h
+++ linux-2.6/drivers/kvm/kvm.h
@@ -9,6 +9,8 @@
 
 #include "vmx.h"
 
+#define KVM_DEBUG 1
+
 #define CR0_PE_MASK (1ULL << 0)
 #define CR0_TS_MASK (1ULL << 3)
 #define CR0_NE_MASK (1ULL << 5)
Index: linux-2.6/drivers/kvm/kvm_main.c
===================================================================
--- linux-2.6.orig/drivers/kvm/kvm_main.c
+++ linux-2.6/drivers/kvm/kvm_main.c
@@ -33,6 +33,7 @@
 
 #include "vmx.h"
 #include "x86_emulate.h"
+#include "debug.h"
 
 MODULE_AUTHOR("Qumranet");
 MODULE_LICENSE("GPL");
@@ -1107,6 +1108,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 	int nr_good_msrs;
 
 
+	printk("*** vcpu_setup begin\n");
+	vmcs_dump(vcpu);
+
 	if (!init_rmode_tss(vcpu->kvm)) {
 		ret = 0;
 		goto out;
@@ -1303,6 +1307,9 @@ static int kvm_vcpu_setup(struct kvm_vcp
 
 	ret = kvm_mmu_init(vcpu);
 
+	printk("*** vcpu_setup end\n");
+	vmcs_dump(vcpu);
+
 	return ret;
 
 out_free_guest_msrs:
@@ -2618,6 +2625,9 @@ again:
 	fx_save(vcpu->host_fx_image);
 	fx_restore(vcpu->guest_fx_image);
 
+	printk("*** pre launch\n");
+	vmcs_dump(vcpu);
+
 	save_msrs(vcpu->host_msrs, vcpu->nmsrs);
 	load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
 
@@ -2740,6 +2750,9 @@ again:
 		[cr2]"i"(offsetof(struct kvm_vcpu, cr2))
 	      : "cc", "memory" );
 
+	printk("*** post launch\n");
+	vmcs_dump(vcpu);
+
 	++kvm_stat.exits;
 
 	save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1: Type: text/plain, Size: 1326 bytes --]

On Tuesday 07 November 2006 15:11, Avi Kivity wrote:
> Hesse, Christian wrote:
> > On Tuesday 07 November 2006 14:25, Avi Kivity wrote:
> >> Hesse, Christian wrote:
> >>> On Tuesday 07 November 2006 13:31, Avi Kivity wrote:
> >>>> Hesse, Christian wrote:
> >>>>>> Then, please apply the attached patch.  You will need serial console
> >>>>>> or netconsole, and to
> >>>>>>
> >>>>>>    echo 9 > /proc/sysrq-trigger
> >>>>>>
> >>>>>> before launching the VM.
> >>>>>
> >>>>> There is no patch attached to this mail...
> >>>>
> >>>> Sorry, attaching now.
> >>>
> >>> There are some undefined values in your code:
> >>>
> >>> /usr/src/kvm-module/debug.c: In function 'vmcs_dump':
> >>> /usr/src/kvm-module/debug.c:924: error: 'HOST_TR_LIMIT' undeclared
> >>> (first use in this function)
> >>
> >> Sorry, refreshed patch attached.
> >
> > Looks better, but you did not catch them all.
>
> Forgot you're using 32-bit.  #ifdef'ed out.

Ok, this one is ok. (Well, it compiles but still crashes my system :)

I will send the log as soon as I get my netconsole to work. I could not yet 
figure out why it does not send any packets.

> Is this machine a laptop?  If so, we may be seeing interaction between
> system management mode and VT.

Yes, this is a Samsung X11 T2300 Culesa.
-- 
Christian

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
>   
>> Is this machine a laptop?  If so, we may be seeing interaction between
>> system management mode and VT.
>>     
>
> Yes, this is a Samsung X11 T2300 Culesa.
>   

Well, bad things happen with laptops, I suspect due to system management 
mode.


Does Xen + VT run on this thing?

-- 
error compiling committee.c: too many arguments to function


-------------------------------------------------------------------------
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1: Type: text/plain, Size: 669 bytes --]

On Wednesday 08 November 2006 09:11, Avi Kivity wrote:
> Hesse, Christian wrote:
> >> Is this machine a laptop?  If so, we may be seeing interaction between
> >> system management mode and VT.
> >
> > Yes, this is a Samsung X11 T2300 Culesa.
>
> Well, bad things happen with laptops, I suspect due to system management
> mode.
>
> Does Xen + VT run on this thing?

Yes, it does. Though it sometimes froze as well, but that was because of 
corrupted disk images, after a fresh install everything worked well again.

As I need at least kernel version 2.6.17 for my notebook to get all the 
drivers I need I stopped playing with it.
-- 
Regards,
Chris

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-------------------------------------------------------------------------
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
> On Wednesday 08 November 2006 09:11, Avi Kivity wrote:
>   
>> Hesse, Christian wrote:
>>     
>>>> Is this machine a laptop?  If so, we may be seeing interaction between
>>>> system management mode and VT.
>>>>         
>>> Yes, this is a Samsung X11 T2300 Culesa.
>>>       
>> Well, bad things happen with laptops, I suspect due to system management
>> mode.
>>
>> Does Xen + VT run on this thing?
>>     
>
> Yes, it does. Though it sometimes froze as well, but that was because of 
> corrupted disk images, after a fresh install everything worked well again.
>   

The host froze due to a corrupted guest image?  That shouldn't happen.

> As I need at least kernel version 2.6.17 for my notebook to get all the 
> drivers I need I stopped playing with it.
>   

Okay.  Please try to apply the two patches I posted yesterday.  I don't 
see how they can help, but it's worth trying.


-- 
error compiling committee.c: too many arguments to function


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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1.1: Type: text/plain, Size: 492 bytes --]

On Wednesday 08 November 2006 09:28, Avi Kivity wrote:
> Okay.  Please try to apply the two patches I posted yesterday.  I don't
> see how they can help, but it's worth trying.

Ok, here is the log. This time the system did not freeze completely, I could 
still move the mouse cursor, grab the qemu window and move that around, too. 
I could not type anything, though I could press Alt+Ctrl+F1 and got a black 
screen and a not blinking (frozen) console cursor.
-- 
Regards,
Chris

[-- Attachment #1.1.2: kvm-qemu.log --]
[-- Type: text/x-log, Size: 8626 bytes --]

*** vcpu_setup begin
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
HOST_CS_SELECTOR 0x0
HOST_DS_SELECTOR 0x0
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
*** vcpu_setup begin
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
************************ vmcs_dump ************************
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
HOST_CR0 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xb17fb340
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x10c90000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x0
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x27c25000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
HOST_IDTR_BASE 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
HOST_CS_SELECTOR 0x0
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
HOST_DS_SELECTOR 0x0
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
HOST_ES_SELECTOR 0x0
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
HOST_FS_SELECTOR 0x0
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
***********************************************************
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x10c90000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x27c25000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x10c90000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x27c25000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
*** pre launch
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
************************ vmcs_dump ************************
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
***********************************************************
HOST_CR0 0x80050033
HOST_CR3 0x10c90000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x27c25000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
***********************************************************

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 373 bytes --]

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[-- Attachment #3: Type: text/plain, Size: 186 bytes --]

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 898 bytes --]

Hesse, Christian wrote:
> On Wednesday 08 November 2006 09:28, Avi Kivity wrote:
>   
>> Okay.  Please try to apply the two patches I posted yesterday.  I don't
>> see how they can help, but it's worth trying.
>>     
>
> Ok, here is the log. This time the system did not freeze completely, I could 
> still move the mouse cursor, grab the qemu window and move that around, too. 
> I could not type anything, though I could press Alt+Ctrl+F1 and got a black 
> screen and a not blinking (frozen) console cursor.
>   

One core was killed, the surviving core was able to run X and service 
some interrupts.

Can you try the attached patch (on top of the previous debug patch)?  In 
addition, please enable pae mode (CONFIG_HIGHMEM64G) to see if the cpu 
has trouble switching from pae mode in the guest to non-pae mode in the 
host.

-- 
error compiling committee.c: too many arguments to function


[-- Attachment #2: kvm-more-debug.patch --]
[-- Type: text/x-patch, Size: 776 bytes --]

Index: linux-2.6/drivers/kvm/debug.c
===================================================================
--- linux-2.6.orig/drivers/kvm/debug.c
+++ linux-2.6/drivers/kvm/debug.c
@@ -997,6 +997,12 @@ void vmcs_dump(struct kvm_vcpu *vcpu)
 
 	vcpu_printf(vcpu, "GUEST_GDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_GDTR_LIMIT));
 	vcpu_printf(vcpu, "GUEST_IDTR_LIMIT 0x%x\n", vmcs_read32(GUEST_IDTR_LIMIT));
+
+	vcpu_printf(vcpu, "VM_EXIT_CONTROLS 0x%x\n", vmcs_read32(VM_EXIT_CONTROLS));
+	vcpu_printf(vcpu, "EXCEPTION_BITMAP 0x%x\n", vmcs_read32(EXCEPTION_BITMAP));
+	vcpu_printf(vcpu, "HOST_RIP 0x%lx\n", vmcs_readl(HOST_RIP));
+	vcpu_printf(vcpu, "HOST_RSP 0x%lx\n", vmcs_readl(HOST_RSP));
+
 	vcpu_printf(vcpu, "***********************************************************\n");
 }
 

[-- Attachment #3: Type: text/plain, Size: 373 bytes --]

-------------------------------------------------------------------------
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[-- Attachment #4: Type: text/plain, Size: 186 bytes --]

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1.1: Type: text/plain, Size: 1028 bytes --]

On Thursday 09 November 2006 14:01, you wrote:
> Hesse, Christian wrote:
> > On Wednesday 08 November 2006 09:28, Avi Kivity wrote:
> >> Okay.  Please try to apply the two patches I posted yesterday.  I don't
> >> see how they can help, but it's worth trying.
> >
> > Ok, here is the log. This time the system did not freeze completely, I
> > could still move the mouse cursor, grab the qemu window and move that
> > around, too. I could not type anything, though I could press Alt+Ctrl+F1
> > and got a black screen and a not blinking (frozen) console cursor.
>
> One core was killed, the surviving core was able to run X and service
> some interrupts.
>
> Can you try the attached patch (on top of the previous debug patch)?  In
> addition, please enable pae mode (CONFIG_HIGHMEM64G) to see if the cpu
> has trouble switching from pae mode in the guest to non-pae mode in the
> host.

The attached patch is with your last patch but without pae mode. I will 
recompile my kernel now.
-- 
Regards,
Chris

[-- Attachment #1.1.2: kvm-qemu.log --]
[-- Type: text/x-log, Size: 9102 bytes --]

*** vcpu_setup begin
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
HOST_CS_SELECTOR 0x0
HOST_DS_SELECTOR 0x0
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
*** vcpu_setup begin
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x21ad5000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x8bf2000
HOST_TR_BASE 0xb17fb340
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
HOST_GDTR_BASE 0xb18ff000
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
HOST_LDTR_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
HOST_IDTR_BASE 0x0
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
HOST_CS_SELECTOR 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
HOST_DS_SELECTOR 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf099e129
HOST_RSP 0x0
***********************************************************
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x21ad5000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x8bf2000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf099e129
HOST_RSP 0x0
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x21ad5000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17f3340
HOST_GDTR_BASE 0xb1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x8bf2000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
*** pre launch
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
************************ vmcs_dump ************************
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_CR0 0x80050033
HOST_RIP 0xf099e129
HOST_RSP 0x0
HOST_CR3 0x21ad5000
***********************************************************
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17f3340
HOST_GDTR_BASE 0xb1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a9000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x8bf2000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf099e129
HOST_RSP 0x0
***********************************************************

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_______________________________________________
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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1.1: Type: text/plain, Size: 513 bytes --]

On Thursday 09 November 2006 14:29, Hesse, Christian wrote:
> On Thursday 09 November 2006 14:01, you wrote:
> > Can you try the attached patch (on top of the previous debug patch)?  In
> > addition, please enable pae mode (CONFIG_HIGHMEM64G) to see if the cpu
> > has trouble switching from pae mode in the guest to non-pae mode in the
> > host.
>
> The attached patch is with your last patch but without pae mode. I will
> recompile my kernel now.

And this one is in pae mode.
-- 
Regards,
Chris

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SysRq : Changing Loglevel
Loglevel set to 9
SysRq : Changing Loglevel
Loglevel set to 9
*** vcpu_setup begin
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
HOST_CS_SELECTOR 0x0
HOST_DS_SELECTOR 0x0
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
*** vcpu_setup begin
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
************************ vmcs_dump ************************
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
HOST_CR0 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x2bcbe000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05ab000
HOST_CS_SELECTOR 0x0
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x0
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x13931000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
HOST_ES_SELECTOR 0x0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
HOST_GS_SELECTOR 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
HOST_SS_SELECTOR 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x2bcbe000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05ab000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x13931000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x2bcbe000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05ab000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x13931000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
*** pre launch
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
************************ vmcs_dump ************************
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_CR0 0x80050033
HOST_RSP 0x0
***********************************************************
HOST_CR3 0x2bcbe000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05ab000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x13931000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
> HOST_CR4 0x2690
> ***********************************************************
> *** pre launch
> ************************ vmcs_dump ************************
> HOST_CR4 0x2690
> GUEST_CR4 0x2021
>   

This doesn't look like pae mode.  Bit 5 of cr4 should be set.  This is 
true for GUEST_CR4 (always so for kvm) but not for HOST_CR4.

One way of checking is

   grep Hugepagesize /proc/meminfo

2MB means pae, 4MB is non-pae.

-- 
error compiling committee.c: too many arguments to function


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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1.1: Type: text/plain, Size: 1995 bytes --]

On Thursday 09 November 2006 14:01, Avi Kivity wrote:
> Hesse, Christian wrote:
> > On Wednesday 08 November 2006 09:28, Avi Kivity wrote:
> >> Okay.  Please try to apply the two patches I posted yesterday.  I don't
> >> see how they can help, but it's worth trying.
> >
> > Ok, here is the log. This time the system did not freeze completely, I
> > could still move the mouse cursor, grab the qemu window and move that
> > around, too. I could not type anything, though I could press Alt+Ctrl+F1
> > and got a black screen and a not blinking (frozen) console cursor.
>
> One core was killed, the surviving core was able to run X and service
> some interrupts.
>
> Can you try the attached patch (on top of the previous debug patch)?  In
> addition, please enable pae mode (CONFIG_HIGHMEM64G) to see if the cpu
> has trouble switching from pae mode in the guest to non-pae mode in the
> host.

You are right this was with CONFIG_HIGHMEM4G, not CONFIG_HIGHMEM*6*4G. Changed 
that in the config an reran the test.

eworm@revo:~$ grep Hugepagesize /proc/meminfo
eworm@revo:~$ cat /proc/meminfo
MemTotal:      1024372 kB
MemFree:        618724 kB
Buffers:            52 kB
Cached:         180756 kB
SwapCached:          0 kB
Active:         222764 kB
Inactive:        89972 kB
HighTotal:      121408 kB
HighFree:          248 kB
LowTotal:       902964 kB
LowFree:        618476 kB
SwapTotal:     2040244 kB
SwapFree:      2040244 kB
Dirty:               4 kB
Writeback:           0 kB
AnonPages:      131968 kB
Mapped:          51216 kB
Slab:            25620 kB
PageTables:       3224 kB
NFS_Unstable:        0 kB
Bounce:              0 kB
CommitLimit:   2552428 kB
Committed_AS:   838332 kB
VmallocTotal:   118776 kB
VmallocUsed:      9768 kB
VmallocChunk:   108660 kB
eworm@revo:~$ gzip -cd /proc/config.gz | grep HIGHMEM
# CONFIG_NOHIGHMEM is not set
# CONFIG_HIGHMEM4G is not set
CONFIG_HIGHMEM64G=y
CONFIG_HIGHMEM=y
-- 
Regards,
Chris

[-- Attachment #1.1.2: kvm-qemu.log --]
[-- Type: text/x-log, Size: 9102 bytes --]

*** vcpu_setup begin
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
HOST_CS_SELECTOR 0x0
HOST_DS_SELECTOR 0x0
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
*** vcpu_setup begin
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
************************ vmcs_dump ************************
GUEST_ES_LIMIT 0x0
HOST_CR0 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
HOST_CR3 0x0
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x19b6200
HOST_CR4 0x26b0
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05af000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_TR_BASE 0xc17f3940
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
HOST_GDTR_BASE 0xc1804000
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x2733c000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
HOST_LDTR_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
HOST_IDTR_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_CS_SELECTOR 0x0
HOST_RIP 0xf919e209
HOST_DS_SELECTOR 0x0
HOST_RSP 0x0
***********************************************************
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x19b6200
HOST_CR4 0x26b0
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05af000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x2733c000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x19b6200
HOST_CR4 0x26b0
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05af000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x2733c000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
*** pre launch
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
************************ vmcs_dump ************************
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
HOST_CR0 0x80050033
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************
HOST_CR3 0x19b6200
HOST_CR4 0x26b0
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xc17f3940
HOST_GDTR_BASE 0xc1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xc05af000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x2733c000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x18850000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf919e209
HOST_RSP 0x0
***********************************************************

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 373 bytes --]

-------------------------------------------------------------------------
Using Tomcat but need to do more? Need to support web services, security?
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[-- Attachment #3: Type: text/plain, Size: 186 bytes --]

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
> You are right this was with CONFIG_HIGHMEM4G, not CONFIG_HIGHMEM*6*4G. Changed 
> that in the config an reran the test.
>
> eworm@revo:~$ grep Hugepagesize /proc/meminfo
>   

You don't have hugetlbfs compiled in.  No matter.

> *** pre launch
> ************************ vmcs_dump ************************
> HOST_CR0 0x80050033
> HOST_CR3 0x19b6200
> HOST_CR4 0x26b0
>   

Now we're in pae mode.

> GUEST_TR_BASE 0x18850000
>   

This looks suspicious.

When I get back to work, I'll see if the TR_BASE really is a problem.  
I'll also send you a userspace test program to start the guest directly 
in 32-bit mode, maybe that will tell us something.


-- 
Do not meddle in the internals of kernels, for they are subtle and quick to panic.


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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Avi Kivity wrote:
>
> Now we're in pae mode.
>
>> GUEST_TR_BASE 0x18850000
>>   
>
> This looks suspicious.

It's actually correct.

>
> When I get back to work, I'll see if the TR_BASE really is a problem.  
> I'll also send you a userspace test program to start the guest 
> directly in 32-bit mode, maybe that will tell us something.
>
>

Please unpack the attached user.tar.gz, and:

cd user
make kvmctl test/test32.flat
sudo ./kvmctl -32 test/test32.flat

(with the kvm module loaded)

the test program tries to execute directly in 32-bit mode, skipping 16-bit.

-- 
error compiling committee.c: too many arguments to function


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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 160 bytes --]

Avi Kivity wrote:
>
> Please unpack the attached user.tar.gz, and:
>
>

Now really attached.


-- 
error compiling committee.c: too many arguments to function


[-- Attachment #2: user.tar.gz --]
[-- Type: application/x-gzip, Size: 163840 bytes --]

[-- Attachment #3: Type: text/plain, Size: 373 bytes --]

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[-- Attachment #4: Type: text/plain, Size: 186 bytes --]

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1.1: Type: text/plain, Size: 734 bytes --]

On Tuesday 14 November 2006 11:41, Avi Kivity wrote:
> Avi Kivity wrote:
> > Now we're in pae mode.
> >
> >> GUEST_TR_BASE 0x18850000
> >
> > This looks suspicious.
>
> It's actually correct.
>
> > When I get back to work, I'll see if the TR_BASE really is a problem.
> > I'll also send you a userspace test program to start the guest
> > directly in 32-bit mode, maybe that will tell us something.
>
> Please unpack the attached user.tar.gz, and:
>
> cd user
> make kvmctl test/test32.flat
> sudo ./kvmctl -32 test/test32.flat
>
> (with the kvm module loaded)
>
> the test program tries to execute directly in 32-bit mode, skipping 16-bit.

It did crash again. The log is attached.
-- 
Regards,
Christian

[-- Attachment #1.1.2: kvm-qemu.log --]
[-- Type: text/x-log, Size: 9136 bytes --]

*** vcpu_setup begin
************************ vmcs_dump ************************
HOST_CR0 0x0
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x0
HOST_IDTR_BASE 0x0
HOST_CS_SELECTOR 0x0
HOST_DS_SELECTOR 0x0
HOST_ES_SELECTOR 0x0
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
*** vcpu_setup begin
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
************************ vmcs_dump ************************
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
HOST_CR0 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
msrs: 1
vmwrite error: reg 2012 value 0 (err 12)
vmwrite error: reg 401c value 0 (err 12)
HOST_CR3 0x0
HOST_CR4 0x0
HOST_TR_SELECTOR 0x0
*** vcpu_setup end
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x3264a000
HOST_CR4 0x2690
HOST_TR_BASE 0xb17fb340
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a7000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x1a26d000
GUEST_CR4 0x2021
HOST_GDTR_BASE 0xb18ff000
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
HOST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
HOST_IDTR_BASE 0x0
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x7ffd000
GUEST_CS_LIMIT 0xffff
HOST_CS_SELECTOR 0x0
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
HOST_DS_SELECTOR 0x0
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf01c8129
HOST_RSP 0x0
HOST_ES_SELECTOR 0x0
***********************************************************
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x0
VM_ENTRY_CONTROLS 0x0
GUEST_CR0 0x0
GUEST_CR3 0x0
GUEST_CR4 0x0
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x0
GUEST_RFLAGS 0x0
GUEST_RIP 0x0
GUEST_CS_SELECTOR 0x0
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0x0
GUEST_DS_AR_BYTES 0x0
GUEST_ES_AR_BYTES 0x0
GUEST_FS_AR_BYTES 0x0
GUEST_GS_AR_BYTES 0x0
GUEST_SS_AR_BYTES 0x0
GUEST_LDTR_AR_BYTES 0x0
GUEST_TR_AR_BYTES 0x0
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0x0
GUEST_DS_LIMIT 0x0
GUEST_ES_LIMIT 0x0
GUEST_FS_LIMIT 0x0
GUEST_GS_LIMIT 0x0
GUEST_SS_LIMIT 0x0
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x0
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x0
EXCEPTION_BITMAP 0x0
HOST_RIP 0x0
HOST_RSP 0x0
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x3264a000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17f3340
HOST_GDTR_BASE 0xb1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a7000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
msrs: 1
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
vmwrite error: reg 2012 value 0 (err 12)
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0x80010037
GUEST_CR3 0x1a26d000
GUEST_CR4 0x2020
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x2
GUEST_RIP 0x100000
GUEST_CS_SELECTOR 0x8
GUEST_DS_SELECTOR 0x10
GUEST_ES_SELECTOR 0x10
vmwrite error: reg 401c value 0 (err 12)
GUEST_FS_SELECTOR 0x10
GUEST_GS_SELECTOR 0x10
GUEST_SS_SELECTOR 0x10
GUEST_TR_SELECTOR 0x18
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xc09b
GUEST_DS_AR_BYTES 0xc093
GUEST_ES_AR_BYTES 0xc093
GUEST_FS_AR_BYTES 0xc093
GUEST_GS_AR_BYTES 0xc093
GUEST_SS_AR_BYTES 0xc093
GUEST_LDTR_AR_BYTES 0x10000
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0x0
*** vcpu_setup end
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
************************ vmcs_dump ************************
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0xffffffff
GUEST_DS_LIMIT 0xffffffff
GUEST_ES_LIMIT 0xffffffff
GUEST_FS_LIMIT 0xffffffff
GUEST_GS_LIMIT 0xffffffff
GUEST_SS_LIMIT 0xffffffff
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x2710
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
HOST_CR0 0x80050033
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0x4000
HOST_RIP 0xf01c8129
HOST_RSP 0x0
***********************************************************
HOST_CR3 0x3264a000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17fb340
HOST_GDTR_BASE 0xb18ff000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a7000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x33
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0xe0010031
GUEST_CR3 0x1a26d000
GUEST_CR4 0x2021
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x23002
GUEST_RIP 0xfff0
GUEST_CS_SELECTOR 0xf000
GUEST_DS_SELECTOR 0x0
GUEST_ES_SELECTOR 0x0
GUEST_FS_SELECTOR 0x0
GUEST_GS_SELECTOR 0x0
GUEST_SS_SELECTOR 0x0
GUEST_TR_SELECTOR 0x0
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xf3
GUEST_DS_AR_BYTES 0xf3
GUEST_ES_AR_BYTES 0xf3
GUEST_FS_AR_BYTES 0xf3
GUEST_GS_AR_BYTES 0xf3
GUEST_SS_AR_BYTES 0xf3
GUEST_LDTR_AR_BYTES 0x82
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0xf0000
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x7ffd000
GUEST_CS_LIMIT 0xffff
GUEST_DS_LIMIT 0xffff
GUEST_ES_LIMIT 0xffff
GUEST_FS_LIMIT 0xffff
GUEST_GS_LIMIT 0xffff
GUEST_SS_LIMIT 0xffff
GUEST_LDTR_LIMIT 0xffff
GUEST_TR_LIMIT 0x2088
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0xffff
GUEST_IDTR_LIMIT 0xffff
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0xffffffff
HOST_RIP 0xf01c8129
HOST_RSP 0x0
***********************************************************
*** pre launch
************************ vmcs_dump ************************
HOST_CR0 0x80050033
HOST_CR3 0x3264a000
HOST_CR4 0x2690
HOST_TR_SELECTOR 0x80
HOST_TR_BASE 0xb17f3340
HOST_GDTR_BASE 0xb1804000
HOST_LDTR_SELECTOR 0x80
HOST_IDTR_BASE 0xb05a7000
HOST_CS_SELECTOR 0x60
HOST_DS_SELECTOR 0x68
HOST_ES_SELECTOR 0x68
HOST_FS_SELECTOR 0x0
HOST_GS_SELECTOR 0x0
HOST_SS_SELECTOR 0x68
VM_ENTRY_CONTROLS 0x11ff
GUEST_CR0 0x80010037
GUEST_CR3 0x1a26d000
GUEST_CR4 0x2020
GUEST_SYSENTER_ESP 0x0
GUEST_SYSENTER_EIP 0x0
GUEST_IA32_DEBUGCTL 0x0
GUEST_DR7 0x400
GUEST_RFLAGS 0x2
GUEST_RIP 0x100000
GUEST_CS_SELECTOR 0x8
GUEST_DS_SELECTOR 0x10
GUEST_ES_SELECTOR 0x10
GUEST_FS_SELECTOR 0x10
GUEST_GS_SELECTOR 0x10
GUEST_SS_SELECTOR 0x10
GUEST_TR_SELECTOR 0x18
GUEST_LDTR_SELECTOR 0x0
GUEST_CS_AR_BYTES 0xc09b
GUEST_DS_AR_BYTES 0xc093
GUEST_ES_AR_BYTES 0xc093
GUEST_FS_AR_BYTES 0xc093
GUEST_GS_AR_BYTES 0xc093
GUEST_SS_AR_BYTES 0xc093
GUEST_LDTR_AR_BYTES 0x10000
GUEST_TR_AR_BYTES 0x8b
GUEST_CS_BASE 0x0
GUEST_DS_BASE 0x0
GUEST_ES_BASE 0x0
GUEST_FS_BASE 0x0
GUEST_GS_BASE 0x0
GUEST_SS_BASE 0x0
GUEST_LDTR_BASE 0x0
GUEST_TR_BASE 0x0
GUEST_CS_LIMIT 0xffffffff
GUEST_DS_LIMIT 0xffffffff
GUEST_ES_LIMIT 0xffffffff
GUEST_FS_LIMIT 0xffffffff
GUEST_GS_LIMIT 0xffffffff
GUEST_SS_LIMIT 0xffffffff
GUEST_LDTR_LIMIT 0x0
GUEST_TR_LIMIT 0x2710
GUEST_GDTR_BASE 0x0
GUEST_IDTR_BASE 0x0
GUEST_GDTR_LIMIT 0x0
GUEST_IDTR_LIMIT 0x0
VM_EXIT_CONTROLS 0x36dff
EXCEPTION_BITMAP 0x4000
HOST_RIP 0xf01c8129
HOST_RSP 0x0
***********************************************************

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Hesse, Christian]

[-- Attachment #1.1: Type: text/plain, Size: 1631 bytes --]

On Thursday 16 November 2006 14:03, Hesse, Christian wrote:
> It did crash again. The log is attached.

I don't know if I already mentioned it, but I think it could be interesting: 
When I reboot the notebook after a crash it starts up normally until X server 
ist started, then it freezes again. Looks like the second core still has any 
problem with its interrupts...

root@revo:~# cat /proc/interrupts
           CPU0       CPU1
  0:   57707101          2    IO-APIC-edge  timer
  1:      26901          0    IO-APIC-edge  i8042
  8:     521165          0    IO-APIC-edge  rtc
  9:      46288          1   IO-APIC-level  acpi
 12:     509781          0    IO-APIC-edge  i8042
 14:     267769          0    IO-APIC-edge  ide0
 16:     714844          0   IO-APIC-level  ipw3945
 17:    4899673    2306254   IO-APIC-level  uhci_hcd:usb5, 
i915@pci:0000:00:02.0, eth0
 18:     439507          0   IO-APIC-level  uhci_hcd:usb4
 19:          0          0   IO-APIC-level  uhci_hcd:usb3
 20:          0          0   IO-APIC-level  yenta
 21:          2          0   IO-APIC-level  ohci1394
 22:          2          0   IO-APIC-level  ehci_hcd:usb1, uhci_hcd:usb2
 23:    1100203          0   IO-APIC-level  sdhci:slot0, HDA Intel
NMI:          0          0
LOC:   57706935   57669244
ERR:          1
MIS:          0
root@revo:~# lspci | grep 00:02.0
00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS/940GML 
Express Integrated Graphics Controller (rev 03)

The second power cycle works without problems though. Do you think that is 
helpful in any way?
-- 
Regards,
Christian

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Re: [PATCH] KVM: fix calculation of initial value of rdx register

[Avi Kivity]

Hesse, Christian wrote:
> On Thursday 16 November 2006 14:03, Hesse, Christian wrote:
>   
>> It did crash again. The log is attached.
>>     
>
> I don't know if I already mentioned it, but I think it could be interesting: 
> When I reboot the notebook after a crash it starts up normally until X server 
> ist started, then it freezes again. Looks like the second core still has any 
> problem with its interrupts...
>
>   

Very strange.


Something to try:

   boot into runlevel 3 (no X)
  
   # bind all processes to cpu 0
   for i in /proc/[1-9]*/task/*; do taskset -p 1 ${i##*/}; done
   # bind all interrupts to cpu 0
   pkill -9 irqbalance
   for i in  /proc/irq/*/smp_affinity; do echo 1 > $i; done   
   # (may give some errors)

   # run kvm with vnc (don't require X)
   ./qemu ... -vnc 1
> root@revo:~# cat /proc/interrupts
>            CPU0       CPU1
>   0:   57707101          2    IO-APIC-edge  timer
>   1:      26901          0    IO-APIC-edge  i8042
>   8:     521165          0    IO-APIC-edge  rtc
>   9:      46288          1   IO-APIC-level  acpi
>  12:     509781          0    IO-APIC-edge  i8042
>  14:     267769          0    IO-APIC-edge  ide0
>  16:     714844          0   IO-APIC-level  ipw3945
>  17:    4899673    2306254   IO-APIC-level  uhci_hcd:usb5, 
> i915@pci:0000:00:02.0, eth0
>  18:     439507          0   IO-APIC-level  uhci_hcd:usb4
>  19:          0          0   IO-APIC-level  uhci_hcd:usb3
>  20:          0          0   IO-APIC-level  yenta
>  21:          2          0   IO-APIC-level  ohci1394
>  22:          2          0   IO-APIC-level  ehci_hcd:usb1, uhci_hcd:usb2
>  23:    1100203          0   IO-APIC-level  sdhci:slot0, HDA Intel
> NMI:          0          0
> LOC:   57706935   57669244
> ERR:          1
> MIS:          0
> root@revo:~# lspci | grep 00:02.0
> 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS/940GML 
> Express Integrated Graphics Controller (rev 03)
>
> The second power cycle works without problems though. Do you think that is 
> helpful in any way?
>   


-- 
error compiling committee.c: too many arguments to function


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