Re: Solaris 10 doesn't work under KVM

Avi Kivity
2007-02-04T09:50:39Z

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Joerg Roedel wrote:
> On Thu, Feb 01, 2007 at 10:49:24PM +0100, Waba wrote:
>
>> On Mon, Jan 29, 2007 at 01:49:06PM +0200, Avi Kivity wrote:
>>
>>> The attached patch should fix it.
>>>
>> Update for those who wouldn't have followed IRC meanwhile: this patch
>> does fix the bug for Opteron-based systems, but doesn't improve anything
>> on my X2 4600+. Avi therefore suggests that someone (_joro?) with
>> knowledge and access to an X2 has a look at it.
>>
>
> I was able to reproduce the bug on a SVM machine here and did some
> deeper research. I intercepted the #UD exception and printed out the
> opcode. This opcode was all zero in the first time and changed randomly
> to other undefined values. I also saved the last exit code before the UD
> intercept and that was a PF intercept. The guest is in 32 bit PAE mode
> when this happens.
> Regarding this research I assume this bug is not SVM related, I think
> something in the MMU goes wrong here.
>
>

kvm-trunk has a fix for this which is both mmu and svm related, see
revision 4348. It seems to fix the exact same problem on opterons but
not on the athlons.

Waba, can you apply the attached patch and post dmesg after the error
occurs? (it also has a small fix which may help).

--
Do not meddle in the internals of kernels, for they are subtle and quick to panic.

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Index: svm.c
===================================================================
--- svm.c (revision 4382)
+++ svm.c (working copy)
@@ -553,7 +553,7 @@
* cr0 val on cpu init should be 0x60000010, we enable cpu
* cache by default. the orderly way is to enable cache in bios.
*/
- save->cr0 = 0x00000010 | CR0_PG_MASK;
+ save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK;
save->cr4 = CR4_PAE_MASK;
/* rdx = ?? */
}
@@ -1430,6 +1430,17 @@
asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
}

+static void check_cr0_wp(struct kvm_vcpu *vcpu, const char *where)
+{
+ static int last_cr0_wp = -1;
+ int cr0_wp;
+
+ cr0_wp = !!(vcpu->svm->vmcb->save.cr0 & CR0_WP_MASK);
+ if (cr0_wp != last_cr0_wp)
+ printk("cr0_wp: %d (%s)\n", cr0_wp, where);
+ last_cr0_wp = cr0_wp;
+}
+
static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
{
u16 fs_selector;
@@ -1463,6 +1474,8 @@
fx_save(vcpu->host_fx_image);
fx_restore(vcpu->guest_fx_image);

+ check_cr0_wp(vcpu, "before");
+
asm volatile (
#ifdef CONFIG_X86_64
"push %%rbx; push %%rcx; push %%rdx;"
@@ -1572,6 +1585,8 @@
#endif
: "cc", "memory" );

+ check_cr0_wp(vcpu, "after");
+
fx_save(vcpu->guest_fx_image);
fx_restore(vcpu->host_fx_image);

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