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From: Brian Johnson <bjj4-xwVYE8SWAR3R7s880joybQ@public.gmane.org>
To: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: PIO port width on various archs?
Date: Mon, 26 Feb 2007 10:52:47 -0600	[thread overview]
Message-ID: <45E3105F.4070303@charter.net> (raw)
In-Reply-To: <45E27A94.3020400-atKUWr5tajBWk0Htik3J/w@public.gmane.org>

Avi Kivity wrote:
> Hollis Blanchard wrote:
>> On Sun, 2007-02-25 at 10:58 +0200, Avi Kivity wrote:
>>   
>>> I'm changing the kvm userspace interface to be more friendly to other 
>>> archs.  One issue is the PIO port size.  x86 uses 16 bits to hold the 
>>> port size (64K ports).  Is that an issue for other archs?
>>>
>>> I guess I could change it to __u32, but it's better to know what various 
>>> architectures actually require.
>>>     
>> PowerPC doesn't have any such concept; access to ISA PIO is done by
>> having the bridge translate a particular range of MMIO accesses as PIO.
>> I'm no expert, but I don't know of any mainstream processor other than
>> x86 that supports PIO.
>>   
> 
> I think ia64 does, but it's probably exactly the same as x86.

IA64 uses a special memory range which is translated into I/O port 
accesses by the CPU hardware (as opposed to the I/O bridge.)  Section 
10.7 of volume 2 of the Itanium SDM has the details.  Only 64k of I/O 
ports is supported.

Brian J. Johnson

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      parent reply	other threads:[~2007-02-26 16:52 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-02-25  8:58 PIO port width on various archs? Avi Kivity
     [not found] ` <45E14F9D.3050502-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
2007-02-26  4:27   ` Hollis Blanchard
2007-02-26  6:13     ` Avi Kivity
     [not found]       ` <45E27A94.3020400-atKUWr5tajBWk0Htik3J/w@public.gmane.org>
2007-02-26 16:52         ` Brian Johnson [this message]

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