Re: PIT weirdness

[Avi Kivity <avi-atKUWr5tajBWk0Htik3J/w@public.gmane.org>]

Gregory Haskins wrote:
> Hi all, 
>   I found some strangeness with the PIT emulation while working on this APIC code that I can't quite explain.  So I thought I would ping the list to see if anyone knowledgable can tell me what is happening. 
>  
> I am seeing two interrupts coming from the PIT for every SIGALARM.  The second interrupt normally gets aliased behind the single vector in the PIC/APIC unless you turn on the TDF feature of QEMU.  I also wrote a "fix" for the in-kernel APIC so it could queue deeper that 1-2 vectors.  In either case, linux now sees time as double time.  Ok, so something is off. 
>  
> Normally I see the PIT ticking at 125Hz.  With the fixes on, I see double that (250Hz).  What I can't explain is: if I look at the PIT registers, "count" is programmed to 4773.  If I do the math correctly, this translates into a 4ms period, or 250Hz. 
>  
> Ok, so it looks like the PIT is *supposed* to be ticking at 250Hz?  If so, why does the system work correctly if every other interrupt is dropped?  This somewhat makes sense because I think Linux uses 250Hz as the default, IIUC (this is a 2.6.16.21 guest) 
>  
> What I figure is that someone hacked in some other compensating logic somewhere else in QEMU so that time passes normally even though jiffies are half speed.  But I would just like someone to sanity check what I described above before attacking from that angle.  Anyone?

Most likely the guest PIT is supposed to tick at 250Hz.  See you .config
to make sure.

There was a fix that was committed to (kvm's) qemu some time ago which
is probably related:

commit 654501f79be082925c623806c00a27021565035f
Author: He, Qing <qing.he-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Date:   Sat Apr 28 09:44:53 2007 +0300

    kvm: qemu: fix PIC interrupt delivery in Qemu when LAPIC is enabled

    Current interrupt logic in Qemu unconditionally checks pending irqs on
    PIC after checking local APIC, however, this is problematic.
        On common platform, PIC is usually connected to the LINT0 of
    local APIC. In this way when local APIC is disabled, this pin behaves
    like INTR. But when local APIC is enabled, its behavior can be
    determined by LVT_LINT0: PIC should only deliver normal irq only when
    `external interrupt' delivery mode is set.
        x86_64 Linux kernel uses PIT->PIC->LINT0 as NMI source when
    performance counters are not available, but the logic described above
    treats the NMI as normal interrupt which yields a 2x faster global timer
    because an additional timer interrupt is injected on every tick. This
    patch fixes this issue.

    Signed-off-by: Qing He <qing.he-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>



-- 
Do not meddle in the internals of kernels, for they are subtle and quick to panic.


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