Re: guest PTE write emulation

Dong, Eddie
2007-05-30T12:48:09Z

Avi Kivity wrote:
> Dong, Eddie wrote:
>> Avi Kivity wrote:
>>
>>> On a pte update, npte will always be 1. On a pde update, we won't
>>> do anything in mmu_pte_write_new_pte because it doesn't handle
>>> pdes. If we extend it to handle pdes, then we need either to
>>> modify the new gpde or to have the update take the quadrant into
>>> account.
>>>
>>
>> Agree, so we either just skip npte=2 branch or polish it. How about
>> following changes?
>>
>
> Isn't it all dead code, as gpte[1] will never be used?

If removing dead code, we can do like following:

diff --git a/drivers/kvm/mmu.c b/drivers/kvm/mmu.c
index c85c664..7d7cd42 100644
--- a/drivers/kvm/mmu.c
+++ b/drivers/kvm/mmu.c
@@ -1209,11 +1209,6 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu,
gpa_t gpa,
* only 2MB. So we need to double the offset
again
* and zap two pdes instead of one.
*/
- if (level == PT32_ROOT_LEVEL) {
- page_offset &= ~7; /* kill rounding
error */
- page_offset <<= 1;
- npte = 2;
- }
quadrant = page_offset >> PAGE_SHIFT;
page_offset &= ~PAGE_MASK;
if (quadrant != page->role.quadrant)

>
> Maybe just move the page->role.level test from mmu_pte_write_new_pte()

role test need to combine with guest CR4 and PS bits.
Current code find about 3.5K times of fake 4M page.

> back to kvm_mmu_pte_write(), so that it's clear that the new
> data isn't
> used for the non-pte case?

Agree.

Eddie