From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anthony Liguori Subject: Re: [PATCH 3/3] Eliminate read_cr3 on TLB flush Date: Thu, 31 May 2007 12:30:27 -0500 Message-ID: <465F0633.7080800@us.ibm.com> References: <97D612E30E1F88419025B06CB4CF1BE10259AD95@scsmsx412.amr.corp.intel.com> <465DCED8.4080506@us.ibm.com> <465E7E4F.8050208@qumranet.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Zachary Amsden , kvm-devel , Anthony Liguori , Jeremy Fitzhardinge , virtualization-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Avi Kivity Return-path: In-Reply-To: <465E7E4F.8050208-atKUWr5tajBWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Avi Kivity wrote: > Anthony Liguori wrote: > >>>> >>>> >>>> >>> For KVM, it should be okay as well. But we can replace two CR4 accesses >>> with just one hypercall. >>> >>> >>> >> I was thinking the same thing :-) >> >> I was actually thinking about adding a hypercall to set/clear a bit in a >> control register. The thought here is that it would be useful not just >> for the global bit but also for CR0.TS although we would need another >> paravirt_op hook for stts. >> >> > > Are global tlb flushes frequent enough to warrant optimization? > I don't think so, so I'm going to remove this from the series. I'm adding another an MMU batching patch which should be enough measurable performance advantage to warrant the series. Regards, Anthony Liguori ------------------------------------------------------------------------- This SF.net email is sponsored by DB2 Express Download DB2 Express C - the FREE version of DB2 express and take control of your XML. No limits. Just data. Click to get it now. http://sourceforge.net/powerbar/db2/