* Duplicate content in files
@ 2007-06-19 20:34 Baruch Even
[not found] ` <46783DC8.2010006-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Baruch Even @ 2007-06-19 20:34 UTC (permalink / raw)
To: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Hello,
I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see that
some files in the kvm sources have the content of the file duplicated,
f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm tree, it
only has it once in qemu as it should be. Look for the include
directives and you'll see what I mean.
There are several other files like that.
Baruch
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Duplicate content in files
[not found] ` <46783DC8.2010006-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
@ 2007-06-19 20:46 ` Luca
[not found] ` <68676e00706191346r615b798emd90be772ac3bdd45-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Luca @ 2007-06-19 20:46 UTC (permalink / raw)
To: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f; +Cc: Baruch Even
On 6/19/07, Baruch Even <baruch-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org> wrote:
> Hello,
>
> I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see that
> some files in the kvm sources have the content of the file duplicated,
> f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm tree, it
> only has it once in qemu as it should be. Look for the include
> directives and you'll see what I mean.
>
> There are several other files like that.
Funny :-) Clearly they're unused in KVM (only x86* is compiled)
otherwise the linker would scream :P
According to GIT those files haven't been touched, something went
wrong during the initial import.
Luca
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Duplicate content in files
[not found] ` <68676e00706191346r615b798emd90be772ac3bdd45-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2007-06-19 20:50 ` Baruch Even
[not found] ` <46784183.4070502-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Baruch Even @ 2007-06-19 20:50 UTC (permalink / raw)
To: Luca; +Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Luca wrote:
> On 6/19/07, Baruch Even <baruch-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org> wrote:
>> Hello,
>>
>> I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see that
>> some files in the kvm sources have the content of the file duplicated,
>> f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm tree, it
>> only has it once in qemu as it should be. Look for the include
>> directives and you'll see what I mean.
>>
>> There are several other files like that.
>
> Funny :-) Clearly they're unused in KVM (only x86* is compiled)
> otherwise the linker would scream :P
> According to GIT those files haven't been touched, something went
> wrong during the initial import.
My problem is that I'm now looking at applying "the kvm patch" into the
Debian qemu so we will remove the need for a special package, in this
case these files will become in use and I'd like to be able to easily
track kvm upstream and update the Debian qemu package.
For this to happen I need the kvm tree to be clean in relation to qemu
and this issue is going to make it a pain to maintain such a patch.
Will the kvm dev folks accept a patch to correct such mistakes?
Baruch
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Duplicate content in files
[not found] ` <46784183.4070502-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
@ 2007-06-19 21:11 ` Anthony Liguori
[not found] ` <46784668.2060106-rdkfGonbjUSkNkDKm+mE6A@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Anthony Liguori @ 2007-06-19 21:11 UTC (permalink / raw)
To: Baruch Even; +Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Baruch Even wrote:
> Luca wrote:
>
>> On 6/19/07, Baruch Even <baruch-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org> wrote:
>>
>>> Hello,
>>>
>>> I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see that
>>> some files in the kvm sources have the content of the file duplicated,
>>> f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm tree, it
>>> only has it once in qemu as it should be. Look for the include
>>> directives and you'll see what I mean.
>>>
>>> There are several other files like that.
>>>
>> Funny :-) Clearly they're unused in KVM (only x86* is compiled)
>> otherwise the linker would scream :P
>> According to GIT those files haven't been touched, something went
>> wrong during the initial import.
>>
>
> My problem is that I'm now looking at applying "the kvm patch" into the
> Debian qemu so we will remove the need for a special package, in this
> case these files will become in use and I'd like to be able to easily
> track kvm upstream and update the Debian qemu package.
>
> For this to happen I need the kvm tree to be clean in relation to qemu
> and this issue is going to make it a pain to maintain such a patch.
>
A patch to eliminate this stuff would be very nice!
Regards,
Anthony Liguori
> Will the kvm dev folks accept a patch to correct such mistakes?
> Baruch
>
> -------------------------------------------------------------------------
> This SF.net email is sponsored by DB2 Express
> Download DB2 Express C - the FREE version of DB2 express and take
> control of your XML. No limits. Just data. Click to get it now.
> http://sourceforge.net/powerbar/db2/
> _______________________________________________
> kvm-devel mailing list
> kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
> https://lists.sourceforge.net/lists/listinfo/kvm-devel
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Duplicate content in files
[not found] ` <46784668.2060106-rdkfGonbjUSkNkDKm+mE6A@public.gmane.org>
@ 2007-06-19 21:36 ` Baruch Even
[not found] ` <46784C46.206-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Baruch Even @ 2007-06-19 21:36 UTC (permalink / raw)
To: Anthony Liguori; +Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
[-- Attachment #1: Type: text/plain, Size: 1319 bytes --]
Anthony Liguori wrote:
> Baruch Even wrote:
>> Luca wrote:
>>
>>> On 6/19/07, Baruch Even <baruch-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org> wrote:
>>>
>>>> Hello,
>>>>
>>>> I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see that
>>>> some files in the kvm sources have the content of the file duplicated,
>>>> f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm tree, it
>>>> only has it once in qemu as it should be. Look for the include
>>>> directives and you'll see what I mean.
>>>>
>>>> There are several other files like that.
>>>>
>>> Funny :-) Clearly they're unused in KVM (only x86* is compiled)
>>> otherwise the linker would scream :P
>>> According to GIT those files haven't been touched, something went
>>> wrong during the initial import.
>>>
>>
>> My problem is that I'm now looking at applying "the kvm patch" into
>> the Debian qemu so we will remove the need for a special package, in
>> this case these files will become in use and I'd like to be able to
>> easily track kvm upstream and update the Debian qemu package.
>>
>> For this to happen I need the kvm tree to be clean in relation to qemu
>> and this issue is going to make it a pain to maintain such a patch.
>>
>
> A patch to eliminate this stuff would be very nice!
Attached.
Baruch
[-- Attachment #2: qemu-dup-removal.patch --]
[-- Type: text/x-patch, Size: 95447 bytes --]
diff --git a/qemu/hw/arm_gic.c b/qemu/hw/arm_gic.c
index 88aa275..2901f34 100644
--- a/qemu/hw/arm_gic.c
+++ b/qemu/hw/arm_gic.c
@@ -545,550 +545,3 @@ void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
gic_reset(s);
return s;
}
-/*
- * ARM AMBA Generic/Distributed Interrupt Controller
- *
- * Copyright (c) 2006 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licenced under the GPL.
- */
-
-/* TODO: Some variants of this controller can handle multiple CPUs.
- Currently only single CPU operation is implemented. */
-
-#include "vl.h"
-#include "arm_pic.h"
-
-//#define DEBUG_GIC
-
-#ifdef DEBUG_GIC
-#define DPRINTF(fmt, args...) \
-do { printf("arm_gic: " fmt , ##args); } while (0)
-#else
-#define DPRINTF(fmt, args...) do {} while(0)
-#endif
-
-/* Distributed interrupt controller. */
-
-static const uint8_t gic_id[] =
-{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
-
-#define GIC_NIRQ 96
-
-typedef struct gic_irq_state
-{
- unsigned enabled:1;
- unsigned pending:1;
- unsigned active:1;
- unsigned level:1;
- unsigned model:1; /* 0 = 1:N, 1 = N:N */
- unsigned trigger:1; /* nonzero = edge triggered. */
-} gic_irq_state;
-
-#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
-#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
-#define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
-#define GIC_SET_PENDING(irq) s->irq_state[irq].pending = 1
-#define GIC_CLEAR_PENDING(irq) s->irq_state[irq].pending = 0
-#define GIC_TEST_PENDING(irq) s->irq_state[irq].pending
-#define GIC_SET_ACTIVE(irq) s->irq_state[irq].active = 1
-#define GIC_CLEAR_ACTIVE(irq) s->irq_state[irq].active = 0
-#define GIC_TEST_ACTIVE(irq) s->irq_state[irq].active
-#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
-#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
-#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
-#define GIC_SET_LEVEL(irq) s->irq_state[irq].level = 1
-#define GIC_CLEAR_LEVEL(irq) s->irq_state[irq].level = 0
-#define GIC_TEST_LEVEL(irq) s->irq_state[irq].level
-#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
-#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
-#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
-
-typedef struct gic_state
-{
- arm_pic_handler handler;
- uint32_t base;
- void *parent;
- int parent_irq;
- int enabled;
- int cpu_enabled;
-
- gic_irq_state irq_state[GIC_NIRQ];
- int irq_target[GIC_NIRQ];
- int priority[GIC_NIRQ];
- int last_active[GIC_NIRQ];
-
- int priority_mask;
- int running_irq;
- int running_priority;
- int current_pending;
-} gic_state;
-
-/* TODO: Many places that call this routine could be optimized. */
-/* Update interrupt status after enabled or pending bits have been changed. */
-static void gic_update(gic_state *s)
-{
- int best_irq;
- int best_prio;
- int irq;
-
- s->current_pending = 1023;
- if (!s->enabled || !s->cpu_enabled) {
- pic_set_irq_new(s->parent, s->parent_irq, 0);
- return;
- }
- best_prio = 0x100;
- best_irq = 1023;
- for (irq = 0; irq < 96; irq++) {
- if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq)) {
- if (s->priority[irq] < best_prio) {
- best_prio = s->priority[irq];
- best_irq = irq;
- }
- }
- }
- if (best_prio > s->priority_mask) {
- pic_set_irq_new(s->parent, s->parent_irq, 0);
- } else {
- s->current_pending = best_irq;
- if (best_prio < s->running_priority) {
- DPRINTF("Raised pending IRQ %d\n", best_irq);
- pic_set_irq_new(s->parent, s->parent_irq, 1);
- }
- }
-}
-
-static void gic_set_irq(void *opaque, int irq, int level)
-{
- gic_state *s = (gic_state *)opaque;
- /* The first external input line is internal interrupt 32. */
- irq += 32;
- if (level == GIC_TEST_LEVEL(irq))
- return;
-
- if (level) {
- GIC_SET_LEVEL(irq);
- if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
- DPRINTF("Set %d pending\n", irq);
- GIC_SET_PENDING(irq);
- }
- } else {
- GIC_CLEAR_LEVEL(irq);
- }
- gic_update(s);
-}
-
-static void gic_set_running_irq(gic_state *s, int irq)
-{
- s->running_irq = irq;
- if (irq == 1023)
- s->running_priority = 0x100;
- else
- s->running_priority = s->priority[irq];
- gic_update(s);
-}
-
-static uint32_t gic_acknowledge_irq(gic_state *s)
-{
- int new_irq;
- new_irq = s->current_pending;
- if (new_irq == 1023 || s->priority[new_irq] >= s->running_priority) {
- DPRINTF("ACK no pending IRQ\n");
- return 1023;
- }
- pic_set_irq_new(s->parent, s->parent_irq, 0);
- s->last_active[new_irq] = s->running_irq;
- /* For level triggered interrupts we clear the pending bit while
- the interrupt is active. */
- GIC_CLEAR_PENDING(new_irq);
- gic_set_running_irq(s, new_irq);
- DPRINTF("ACK %d\n", new_irq);
- return new_irq;
-}
-
-static void gic_complete_irq(gic_state * s, int irq)
-{
- int update = 0;
- DPRINTF("EOI %d\n", irq);
- if (s->running_irq == 1023)
- return; /* No active IRQ. */
- if (irq != 1023) {
- /* Mark level triggered interrupts as pending if they are still
- raised. */
- if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
- && GIC_TEST_LEVEL(irq)) {
- GIC_SET_PENDING(irq);
- update = 1;
- }
- }
- if (irq != s->running_irq) {
- /* Complete an IRQ that is not currently running. */
- int tmp = s->running_irq;
- while (s->last_active[tmp] != 1023) {
- if (s->last_active[tmp] == irq) {
- s->last_active[tmp] = s->last_active[irq];
- break;
- }
- tmp = s->last_active[tmp];
- }
- if (update) {
- gic_update(s);
- }
- } else {
- /* Complete the current running IRQ. */
- gic_set_running_irq(s, s->last_active[s->running_irq]);
- }
-}
-
-static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
-{
- gic_state *s = (gic_state *)opaque;
- uint32_t res;
- int irq;
- int i;
-
- offset -= s->base + 0x1000;
- if (offset < 0x100) {
- if (offset == 0)
- return s->enabled;
- if (offset == 4)
- return (GIC_NIRQ / 32) - 1;
- if (offset < 0x08)
- return 0;
- goto bad_reg;
- } else if (offset < 0x200) {
- /* Interrupt Set/Clear Enable. */
- if (offset < 0x180)
- irq = (offset - 0x100) * 8;
- else
- irq = (offset - 0x180) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = 0;
- for (i = 0; i < 8; i++) {
- if (GIC_TEST_ENABLED(irq + i)) {
- res |= (1 << i);
- }
- }
- } else if (offset < 0x300) {
- /* Interrupt Set/Clear Pending. */
- if (offset < 0x280)
- irq = (offset - 0x200) * 8;
- else
- irq = (offset - 0x280) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = 0;
- for (i = 0; i < 8; i++) {
- if (GIC_TEST_PENDING(irq + i)) {
- res |= (1 << i);
- }
- }
- } else if (offset < 0x400) {
- /* Interrupt Active. */
- irq = (offset - 0x300) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = 0;
- for (i = 0; i < 8; i++) {
- if (GIC_TEST_ACTIVE(irq + i)) {
- res |= (1 << i);
- }
- }
- } else if (offset < 0x800) {
- /* Interrupt Priority. */
- irq = offset - 0x400;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = s->priority[irq];
- } else if (offset < 0xc00) {
- /* Interrupt CPU Target. */
- irq = offset - 0x800;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = s->irq_target[irq];
- } else if (offset < 0xf00) {
- /* Interrupt Configuration. */
- irq = (offset - 0xc00) * 2;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- res = 0;
- for (i = 0; i < 4; i++) {
- if (GIC_TEST_MODEL(irq + i))
- res |= (1 << (i * 2));
- if (GIC_TEST_TRIGGER(irq + i))
- res |= (2 << (i * 2));
- }
- } else if (offset < 0xfe0) {
- goto bad_reg;
- } else /* offset >= 0xfe0 */ {
- if (offset & 3) {
- res = 0;
- } else {
- res = gic_id[(offset - 0xfe0) >> 2];
- }
- }
- return res;
-bad_reg:
- cpu_abort (cpu_single_env, "gic_dist_readb: Bad offset %x\n", offset);
- return 0;
-}
-
-static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
-{
- uint32_t val;
- val = gic_dist_readb(opaque, offset);
- val |= gic_dist_readb(opaque, offset + 1) << 8;
- return val;
-}
-
-static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
-{
- uint32_t val;
- val = gic_dist_readw(opaque, offset);
- val |= gic_dist_readw(opaque, offset + 2) << 16;
- return val;
-}
-
-static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
- uint32_t value)
-{
- gic_state *s = (gic_state *)opaque;
- int irq;
- int i;
-
- offset -= s->base + 0x1000;
- if (offset < 0x100) {
- if (offset == 0) {
- s->enabled = (value & 1);
- DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
- } else if (offset < 4) {
- /* ignored. */
- } else {
- goto bad_reg;
- }
- } else if (offset < 0x180) {
- /* Interrupt Set Enable. */
- irq = (offset - 0x100) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- for (i = 0; i < 8; i++) {
- if (value & (1 << i)) {
- if (!GIC_TEST_ENABLED(irq + i))
- DPRINTF("Enabled IRQ %d\n", irq + i);
- GIC_SET_ENABLED(irq + i);
- /* If a raised level triggered IRQ enabled then mark
- is as pending. */
- if (GIC_TEST_LEVEL(irq + i) && !GIC_TEST_TRIGGER(irq + i))
- GIC_SET_PENDING(irq + i);
- }
- }
- } else if (offset < 0x200) {
- /* Interrupt Clear Enable. */
- irq = (offset - 0x180) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- for (i = 0; i < 8; i++) {
- if (value & (1 << i)) {
- if (GIC_TEST_ENABLED(irq + i))
- DPRINTF("Disabled IRQ %d\n", irq + i);
- GIC_CLEAR_ENABLED(irq + i);
- }
- }
- } else if (offset < 0x280) {
- /* Interrupt Set Pending. */
- irq = (offset - 0x200) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- for (i = 0; i < 8; i++) {
- if (value & (1 << i)) {
- GIC_SET_PENDING(irq + i);
- }
- }
- } else if (offset < 0x300) {
- /* Interrupt Clear Pending. */
- irq = (offset - 0x280) * 8;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- for (i = 0; i < 8; i++) {
- if (value & (1 << i)) {
- GIC_CLEAR_PENDING(irq + i);
- }
- }
- } else if (offset < 0x400) {
- /* Interrupt Active. */
- goto bad_reg;
- } else if (offset < 0x800) {
- /* Interrupt Priority. */
- irq = offset - 0x400;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- s->priority[irq] = value;
- } else if (offset < 0xc00) {
- /* Interrupt CPU Target. */
- irq = offset - 0x800;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- s->irq_target[irq] = value;
- } else if (offset < 0xf00) {
- /* Interrupt Configuration. */
- irq = (offset - 0xc00) * 4;
- if (irq >= GIC_NIRQ)
- goto bad_reg;
- for (i = 0; i < 4; i++) {
- if (value & (1 << (i * 2))) {
- GIC_SET_MODEL(irq + i);
- } else {
- GIC_CLEAR_MODEL(irq + i);
- }
- if (value & (2 << (i * 2))) {
- GIC_SET_TRIGGER(irq + i);
- } else {
- GIC_CLEAR_TRIGGER(irq + i);
- }
- }
- } else {
- /* 0xf00 is only handled for word writes. */
- goto bad_reg;
- }
- gic_update(s);
- return;
-bad_reg:
- cpu_abort (cpu_single_env, "gic_dist_writeb: Bad offset %x\n", offset);
-}
-
-static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
- uint32_t value)
-{
- gic_state *s = (gic_state *)opaque;
- if (offset - s->base == 0xf00) {
- GIC_SET_PENDING(value & 0x3ff);
- gic_update(s);
- return;
- }
- gic_dist_writeb(opaque, offset, value & 0xff);
- gic_dist_writeb(opaque, offset + 1, value >> 8);
-}
-
-static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
- uint32_t value)
-{
- gic_dist_writew(opaque, offset, value & 0xffff);
- gic_dist_writew(opaque, offset + 2, value >> 16);
-}
-
-static CPUReadMemoryFunc *gic_dist_readfn[] = {
- gic_dist_readb,
- gic_dist_readw,
- gic_dist_readl
-};
-
-static CPUWriteMemoryFunc *gic_dist_writefn[] = {
- gic_dist_writeb,
- gic_dist_writew,
- gic_dist_writel
-};
-
-static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset)
-{
- gic_state *s = (gic_state *)opaque;
- offset -= s->base;
- switch (offset) {
- case 0x00: /* Control */
- return s->cpu_enabled;
- case 0x04: /* Priority mask */
- return s->priority_mask;
- case 0x08: /* Binary Point */
- /* ??? Not implemented. */
- return 0;
- case 0x0c: /* Acknowledge */
- return gic_acknowledge_irq(s);
- case 0x14: /* Runing Priority */
- return s->running_priority;
- case 0x18: /* Highest Pending Interrupt */
- return s->current_pending;
- default:
- cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
- return 0;
- }
-}
-
-static void gic_cpu_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
-{
- gic_state *s = (gic_state *)opaque;
- offset -= s->base;
- switch (offset) {
- case 0x00: /* Control */
- s->cpu_enabled = (value & 1);
- DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
- break;
- case 0x04: /* Priority mask */
- s->priority_mask = (value & 0x3ff);
- break;
- case 0x08: /* Binary Point */
- /* ??? Not implemented. */
- break;
- case 0x10: /* End Of Interrupt */
- return gic_complete_irq(s, value & 0x3ff);
- default:
- cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
- return;
- }
- gic_update(s);
-}
-
-static CPUReadMemoryFunc *gic_cpu_readfn[] = {
- gic_cpu_read,
- gic_cpu_read,
- gic_cpu_read
-};
-
-static CPUWriteMemoryFunc *gic_cpu_writefn[] = {
- gic_cpu_write,
- gic_cpu_write,
- gic_cpu_write
-};
-
-static void gic_reset(gic_state *s)
-{
- int i;
- memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
- s->priority_mask = 0xf0;
- s->current_pending = 1023;
- s->running_irq = 1023;
- s->running_priority = 0x100;
- for (i = 0; i < 15; i++) {
- GIC_SET_ENABLED(i);
- GIC_SET_TRIGGER(i);
- }
- s->enabled = 0;
- s->cpu_enabled = 0;
-}
-
-void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
-{
- gic_state *s;
- int iomemtype;
-
- s = (gic_state *)qemu_mallocz(sizeof(gic_state));
- if (!s)
- return NULL;
- s->handler = gic_set_irq;
- s->parent = parent;
- s->parent_irq = parent_irq;
- if (base != 0xffffffff) {
- iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
- gic_cpu_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
- iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
- gic_dist_writefn, s);
- cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype);
- s->base = base;
- } else {
- s->base = 0;
- }
- gic_reset(s);
- return s;
-}
diff --git a/qemu/hw/arm_sysctl.c b/qemu/hw/arm_sysctl.c
index e633f5d..e9de998 100644
--- a/qemu/hw/arm_sysctl.c
+++ b/qemu/hw/arm_sysctl.c
@@ -206,211 +206,3 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id)
/* ??? Save/restore. */
}
-/*
- * Status and system control registers for ARM RealView/Versatile boards.
- *
- * Copyright (c) 2006 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licenced under the GPL.
- */
-
-#include "vl.h"
-#include "arm_pic.h"
-
-#define LOCK_VALUE 0xa05f
-
-typedef struct {
- uint32_t base;
- uint32_t sys_id;
- uint32_t leds;
- uint16_t lockval;
- uint32_t cfgdata1;
- uint32_t cfgdata2;
- uint32_t flags;
- uint32_t nvflags;
- uint32_t resetlevel;
-} arm_sysctl_state;
-
-static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
-{
- arm_sysctl_state *s = (arm_sysctl_state *)opaque;
-
- offset -= s->base;
- switch (offset) {
- case 0x00: /* ID */
- return s->sys_id;
- case 0x04: /* SW */
- /* General purpose hardware switches.
- We don't have a useful way of exposing these to the user. */
- return 0;
- case 0x08: /* LED */
- return s->leds;
- case 0x20: /* LOCK */
- return s->lockval;
- case 0x0c: /* OSC0 */
- case 0x10: /* OSC1 */
- case 0x14: /* OSC2 */
- case 0x18: /* OSC3 */
- case 0x1c: /* OSC4 */
- case 0x24: /* 100HZ */
- /* ??? Implement these. */
- return 0;
- case 0x28: /* CFGDATA1 */
- return s->cfgdata1;
- case 0x2c: /* CFGDATA2 */
- return s->cfgdata2;
- case 0x30: /* FLAGS */
- return s->flags;
- case 0x38: /* NVFLAGS */
- return s->nvflags;
- case 0x40: /* RESETCTL */
- return s->resetlevel;
- case 0x44: /* PCICTL */
- return 1;
- case 0x48: /* MCI */
- return 0;
- case 0x4c: /* FLASH */
- return 0;
- case 0x50: /* CLCD */
- return 0x1000;
- case 0x54: /* CLCDSER */
- return 0;
- case 0x58: /* BOOTCS */
- return 0;
- case 0x5c: /* 24MHz */
- /* ??? not implemented. */
- return 0;
- case 0x60: /* MISC */
- return 0;
- case 0x84: /* PROCID0 */
- /* ??? Don't know what the proper value for the core tile ID is. */
- return 0x02000000;
- case 0x88: /* PROCID1 */
- return 0xff000000;
- case 0x64: /* DMAPSR0 */
- case 0x68: /* DMAPSR1 */
- case 0x6c: /* DMAPSR2 */
- case 0x70: /* IOSEL */
- case 0x74: /* PLDCTL */
- case 0x80: /* BUSID */
- case 0x8c: /* OSCRESET0 */
- case 0x90: /* OSCRESET1 */
- case 0x94: /* OSCRESET2 */
- case 0x98: /* OSCRESET3 */
- case 0x9c: /* OSCRESET4 */
- case 0xc0: /* SYS_TEST_OSC0 */
- case 0xc4: /* SYS_TEST_OSC1 */
- case 0xc8: /* SYS_TEST_OSC2 */
- case 0xcc: /* SYS_TEST_OSC3 */
- case 0xd0: /* SYS_TEST_OSC4 */
- return 0;
- default:
- printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
- return 0;
- }
-}
-
-static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
- uint32_t val)
-{
- arm_sysctl_state *s = (arm_sysctl_state *)opaque;
- offset -= s->base;
-
- switch (offset) {
- case 0x08: /* LED */
- s->leds = val;
- case 0x0c: /* OSC0 */
- case 0x10: /* OSC1 */
- case 0x14: /* OSC2 */
- case 0x18: /* OSC3 */
- case 0x1c: /* OSC4 */
- /* ??? */
- break;
- case 0x20: /* LOCK */
- if (val == LOCK_VALUE)
- s->lockval = val;
- else
- s->lockval = val & 0x7fff;
- break;
- case 0x28: /* CFGDATA1 */
- /* ??? Need to implement this. */
- s->cfgdata1 = val;
- break;
- case 0x2c: /* CFGDATA2 */
- /* ??? Need to implement this. */
- s->cfgdata2 = val;
- break;
- case 0x30: /* FLAGSSET */
- s->flags |= val;
- break;
- case 0x34: /* FLAGSCLR */
- s->flags &= ~val;
- break;
- case 0x38: /* NVFLAGSSET */
- s->nvflags |= val;
- break;
- case 0x3c: /* NVFLAGSCLR */
- s->nvflags &= ~val;
- break;
- case 0x40: /* RESETCTL */
- if (s->lockval == LOCK_VALUE) {
- s->resetlevel = val;
- if (val & 0x100)
- cpu_abort(cpu_single_env, "Board reset\n");
- }
- break;
- case 0x44: /* PCICTL */
- /* nothing to do. */
- break;
- case 0x4c: /* FLASH */
- case 0x50: /* CLCD */
- case 0x54: /* CLCDSER */
- case 0x64: /* DMAPSR0 */
- case 0x68: /* DMAPSR1 */
- case 0x6c: /* DMAPSR2 */
- case 0x70: /* IOSEL */
- case 0x74: /* PLDCTL */
- case 0x80: /* BUSID */
- case 0x84: /* PROCID0 */
- case 0x88: /* PROCID1 */
- case 0x8c: /* OSCRESET0 */
- case 0x90: /* OSCRESET1 */
- case 0x94: /* OSCRESET2 */
- case 0x98: /* OSCRESET3 */
- case 0x9c: /* OSCRESET4 */
- break;
- default:
- printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
- return;
- }
-}
-
-static CPUReadMemoryFunc *arm_sysctl_readfn[] = {
- arm_sysctl_read,
- arm_sysctl_read,
- arm_sysctl_read
-};
-
-static CPUWriteMemoryFunc *arm_sysctl_writefn[] = {
- arm_sysctl_write,
- arm_sysctl_write,
- arm_sysctl_write
-};
-
-void arm_sysctl_init(uint32_t base, uint32_t sys_id)
-{
- arm_sysctl_state *s;
- int iomemtype;
-
- s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state));
- if (!s)
- return;
- s->base = base;
- s->sys_id = sys_id;
- iomemtype = cpu_register_io_memory(0, arm_sysctl_readfn,
- arm_sysctl_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
- /* ??? Save/restore. */
-}
-
diff --git a/qemu/hw/cs4231.c b/qemu/hw/cs4231.c
index 9aa2a83..a154685 100644
--- a/qemu/hw/cs4231.c
+++ b/qemu/hw/cs4231.c
@@ -181,186 +181,3 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
qemu_register_reset(cs_reset, s);
cs_reset(s);
}
-/*
- * QEMU Crystal CS4231 audio chip emulation
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include "vl.h"
-
-/* debug CS4231 */
-//#define DEBUG_CS
-
-/*
- * In addition to Crystal CS4231 there is a DMA controller on Sparc.
- */
-#define CS_MAXADDR 0x3f
-#define CS_REGS 16
-#define CS_DREGS 32
-#define CS_MAXDREG (CS_DREGS - 1)
-
-typedef struct CSState {
- uint32_t regs[CS_REGS];
- uint8_t dregs[CS_DREGS];
- void *intctl;
-} CSState;
-
-#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
-#define CS_VER 0xa0
-#define CS_CDC_VER 0x8a
-
-#ifdef DEBUG_CS
-#define DPRINTF(fmt, args...) \
- do { printf("CS: " fmt , ##args); } while (0)
-#define pic_set_irq_new(intctl, irq, level) \
- do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \
- pic_set_irq_new((intctl), (irq),(level));} while (0)
-#else
-#define DPRINTF(fmt, args...)
-#endif
-
-static void cs_reset(void *opaque)
-{
- CSState *s = opaque;
-
- memset(s->regs, 0, CS_REGS * 4);
- memset(s->dregs, 0, CS_DREGS);
- s->dregs[12] = CS_CDC_VER;
- s->dregs[25] = CS_VER;
-}
-
-static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
-{
- CSState *s = opaque;
- uint32_t saddr, ret;
-
- saddr = (addr & CS_MAXADDR) >> 2;
- switch (saddr) {
- case 1:
- switch (CS_RAP(s)) {
- case 3: // Write only
- ret = 0;
- break;
- default:
- ret = s->dregs[CS_RAP(s)];
- break;
- }
- DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
- break;
- default:
- ret = s->regs[saddr];
- DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
- break;
- }
- return ret;
-}
-
-static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- CSState *s = opaque;
- uint32_t saddr;
-
- saddr = (addr & CS_MAXADDR) >> 2;
- DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
- switch (saddr) {
- case 1:
- DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
- switch(CS_RAP(s)) {
- case 11:
- case 25: // Read only
- break;
- case 12:
- val &= 0x40;
- val |= CS_CDC_VER; // Codec version
- s->dregs[CS_RAP(s)] = val;
- break;
- default:
- s->dregs[CS_RAP(s)] = val;
- break;
- }
- break;
- case 2: // Read only
- break;
- case 4:
- if (val & 1)
- cs_reset(s);
- val &= 0x7f;
- s->regs[saddr] = val;
- break;
- default:
- s->regs[saddr] = val;
- break;
- }
-}
-
-static CPUReadMemoryFunc *cs_mem_read[3] = {
- cs_mem_readl,
- cs_mem_readl,
- cs_mem_readl,
-};
-
-static CPUWriteMemoryFunc *cs_mem_write[3] = {
- cs_mem_writel,
- cs_mem_writel,
- cs_mem_writel,
-};
-
-static void cs_save(QEMUFile *f, void *opaque)
-{
- CSState *s = opaque;
- unsigned int i;
-
- for (i = 0; i < CS_REGS; i++)
- qemu_put_be32s(f, &s->regs[i]);
-
- qemu_put_buffer(f, s->dregs, CS_DREGS);
-}
-
-static int cs_load(QEMUFile *f, void *opaque, int version_id)
-{
- CSState *s = opaque;
- unsigned int i;
-
- if (version_id > 1)
- return -EINVAL;
-
- for (i = 0; i < CS_REGS; i++)
- qemu_get_be32s(f, &s->regs[i]);
-
- qemu_get_buffer(f, s->dregs, CS_DREGS);
- return 0;
-}
-
-void cs_init(target_phys_addr_t base, int irq, void *intctl)
-{
- int cs_io_memory;
- CSState *s;
-
- s = qemu_mallocz(sizeof(CSState));
- if (!s)
- return;
-
- cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
- cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
- register_savevm("cs4231", base, 1, cs_save, cs_load, s);
- qemu_register_reset(cs_reset, s);
- cs_reset(s);
-}
diff --git a/qemu/hw/gt64xxx.c b/qemu/hw/gt64xxx.c
index b03ed58..ccb6a7c 100644
--- a/qemu/hw/gt64xxx.c
+++ b/qemu/hw/gt64xxx.c
@@ -646,651 +646,3 @@ PCIBus *pci_gt64120_init(void *pic)
return s->pci->bus;
}
-/*
- * QEMU GT64120 PCI host
- *
- * Copyright (c) 2006,2007 Aurelien Jarno
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "vl.h"
-typedef target_phys_addr_t pci_addr_t;
-#include "pci_host.h"
-
-#define GT_REGS (0x1000 >> 2)
-
-/* CPU Configuration */
-#define GT_CPU (0x000 >> 2)
-#define GT_MULTI (0x120 >> 2)
-
-/* CPU Address Decode */
-#define GT_SCS10LD (0x008 >> 2)
-#define GT_SCS10HD (0x010 >> 2)
-#define GT_SCS32LD (0x018 >> 2)
-#define GT_SCS32HD (0x020 >> 2)
-#define GT_CS20LD (0x028 >> 2)
-#define GT_CS20HD (0x030 >> 2)
-#define GT_CS3BOOTLD (0x038 >> 2)
-#define GT_CS3BOOTHD (0x040 >> 2)
-#define GT_PCI0IOLD (0x048 >> 2)
-#define GT_PCI0IOHD (0x050 >> 2)
-#define GT_PCI0M0LD (0x058 >> 2)
-#define GT_PCI0M0HD (0x060 >> 2)
-#define GT_ISD (0x068 >> 2)
-
-#define GT_PCI0M1LD (0x080 >> 2)
-#define GT_PCI0M1HD (0x088 >> 2)
-#define GT_PCI1IOLD (0x090 >> 2)
-#define GT_PCI1IOHD (0x098 >> 2)
-#define GT_PCI1M0LD (0x0a0 >> 2)
-#define GT_PCI1M0HD (0x0a8 >> 2)
-#define GT_PCI1M1LD (0x0b0 >> 2)
-#define GT_PCI1M1HD (0x0b8 >> 2)
-#define GT_PCI1M1LD (0x0b0 >> 2)
-#define GT_PCI1M1HD (0x0b8 >> 2)
-
-#define GT_SCS10AR (0x0d0 >> 2)
-#define GT_SCS32AR (0x0d8 >> 2)
-#define GT_CS20R (0x0e0 >> 2)
-#define GT_CS3BOOTR (0x0e8 >> 2)
-
-#define GT_PCI0IOREMAP (0x0f0 >> 2)
-#define GT_PCI0M0REMAP (0x0f8 >> 2)
-#define GT_PCI0M1REMAP (0x100 >> 2)
-#define GT_PCI1IOREMAP (0x108 >> 2)
-#define GT_PCI1M0REMAP (0x110 >> 2)
-#define GT_PCI1M1REMAP (0x118 >> 2)
-
-/* CPU Error Report */
-#define GT_CPUERR_ADDRLO (0x070 >> 2)
-#define GT_CPUERR_ADDRHI (0x078 >> 2)
-#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
-#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
-#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
-
-/* CPU Sync Barrier */
-#define GT_PCI0SYNC (0x0c0 >> 2)
-#define GT_PCI1SYNC (0x0c8 >> 2)
-
-/* SDRAM and Device Address Decode */
-#define GT_SCS0LD (0x400 >> 2)
-#define GT_SCS0HD (0x404 >> 2)
-#define GT_SCS1LD (0x408 >> 2)
-#define GT_SCS1HD (0x40c >> 2)
-#define GT_SCS2LD (0x410 >> 2)
-#define GT_SCS2HD (0x414 >> 2)
-#define GT_SCS3LD (0x418 >> 2)
-#define GT_SCS3HD (0x41c >> 2)
-#define GT_CS0LD (0x420 >> 2)
-#define GT_CS0HD (0x424 >> 2)
-#define GT_CS1LD (0x428 >> 2)
-#define GT_CS1HD (0x42c >> 2)
-#define GT_CS2LD (0x430 >> 2)
-#define GT_CS2HD (0x434 >> 2)
-#define GT_CS3LD (0x438 >> 2)
-#define GT_CS3HD (0x43c >> 2)
-#define GT_BOOTLD (0x440 >> 2)
-#define GT_BOOTHD (0x444 >> 2)
-#define GT_ADERR (0x470 >> 2)
-
-/* SDRAM Configuration */
-#define GT_SDRAM_CFG (0x448 >> 2)
-#define GT_SDRAM_OPMODE (0x474 >> 2)
-#define GT_SDRAM_BM (0x478 >> 2)
-#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
-
-/* SDRAM Parameters */
-#define GT_SDRAM_B0 (0x44c >> 2)
-#define GT_SDRAM_B1 (0x450 >> 2)
-#define GT_SDRAM_B2 (0x454 >> 2)
-#define GT_SDRAM_B3 (0x458 >> 2)
-
-/* Device Parameters */
-#define GT_DEV_B0 (0x45c >> 2)
-#define GT_DEV_B1 (0x460 >> 2)
-#define GT_DEV_B2 (0x464 >> 2)
-#define GT_DEV_B3 (0x468 >> 2)
-#define GT_DEV_BOOT (0x46c >> 2)
-
-/* ECC */
-#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
-#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
-#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
-#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
-#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
-
-/* DMA Record */
-#define GT_DMA0_CNT (0x800 >> 2)
-#define GT_DMA1_CNT (0x804 >> 2)
-#define GT_DMA2_CNT (0x808 >> 2)
-#define GT_DMA3_CNT (0x80c >> 2)
-#define GT_DMA0_SA (0x810 >> 2)
-#define GT_DMA1_SA (0x814 >> 2)
-#define GT_DMA2_SA (0x818 >> 2)
-#define GT_DMA3_SA (0x81c >> 2)
-#define GT_DMA0_DA (0x820 >> 2)
-#define GT_DMA1_DA (0x824 >> 2)
-#define GT_DMA2_DA (0x828 >> 2)
-#define GT_DMA3_DA (0x82c >> 2)
-#define GT_DMA0_NEXT (0x830 >> 2)
-#define GT_DMA1_NEXT (0x834 >> 2)
-#define GT_DMA2_NEXT (0x838 >> 2)
-#define GT_DMA3_NEXT (0x83c >> 2)
-#define GT_DMA0_CUR (0x870 >> 2)
-#define GT_DMA1_CUR (0x874 >> 2)
-#define GT_DMA2_CUR (0x878 >> 2)
-#define GT_DMA3_CUR (0x87c >> 2)
-
-/* DMA Channel Control */
-#define GT_DMA0_CTRL (0x840 >> 2)
-#define GT_DMA1_CTRL (0x844 >> 2)
-#define GT_DMA2_CTRL (0x848 >> 2)
-#define GT_DMA3_CTRL (0x84c >> 2)
-
-/* DMA Arbiter */
-#define GT_DMA_ARB (0x860 >> 2)
-
-/* Timer/Counter */
-#define GT_TC0 (0x850 >> 2)
-#define GT_TC1 (0x854 >> 2)
-#define GT_TC2 (0x858 >> 2)
-#define GT_TC3 (0x85c >> 2)
-#define GT_TC_CONTROL (0x864 >> 2)
-
-/* PCI Internal */
-#define GT_PCI0_CMD (0xc00 >> 2)
-#define GT_PCI0_TOR (0xc04 >> 2)
-#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
-#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
-#define GT_PCI0_BS_CS20 (0xc10 >> 2)
-#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
-#define GT_PCI1_IACK (0xc30 >> 2)
-#define GT_PCI0_IACK (0xc34 >> 2)
-#define GT_PCI0_BARE (0xc3c >> 2)
-#define GT_PCI0_PREFMBR (0xc40 >> 2)
-#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
-#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
-#define GT_PCI0_CS20_BAR (0xc50 >> 2)
-#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
-#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
-#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
-#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
-#define GT_PCI1_CMD (0xc80 >> 2)
-#define GT_PCI1_TOR (0xc84 >> 2)
-#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
-#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
-#define GT_PCI1_BS_CS20 (0xc90 >> 2)
-#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
-#define GT_PCI1_BARE (0xcbc >> 2)
-#define GT_PCI1_PREFMBR (0xcc0 >> 2)
-#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
-#define GT_PCI1_SCS32_BAR (0xccc >> 2)
-#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
-#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
-#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
-#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
-#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
-#define GT_PCI1_CFGADDR (0xcf0 >> 2)
-#define GT_PCI1_CFGDATA (0xcf4 >> 2)
-#define GT_PCI0_CFGADDR (0xcf8 >> 2)
-#define GT_PCI0_CFGDATA (0xcfc >> 2)
-
-/* Interrupts */
-#define GT_INTRCAUSE (0xc18 >> 2)
-#define GT_INTRMASK (0xc1c >> 2)
-#define GT_PCI0_ICMASK (0xc24 >> 2)
-#define GT_PCI0_SERR0MASK (0xc28 >> 2)
-#define GT_CPU_INTSEL (0xc70 >> 2)
-#define GT_PCI0_INTSEL (0xc74 >> 2)
-#define GT_HINTRCAUSE (0xc98 >> 2)
-#define GT_HINTRMASK (0xc9c >> 2)
-#define GT_PCI0_HICMASK (0xca4 >> 2)
-#define GT_PCI1_SERR1MASK (0xca8 >> 2)
-
-
-typedef PCIHostState GT64120PCIState;
-
-typedef struct GT64120State {
- GT64120PCIState *pci;
- uint32_t regs[GT_REGS];
-} GT64120State;
-
-static void gt64120_pci_mapping(GT64120State *s)
-{
- target_phys_addr_t start, length;
-
- /* Update IO mapping */
- if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
- {
- start = s->regs[GT_PCI0IOLD] << 21;
- length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
- isa_mmio_init(start, length);
- }
-}
-
-static void gt64120_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- GT64120State *s = opaque;
- uint32_t saddr;
-
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
-
- saddr = (addr & 0xfff) >> 2;
- switch (saddr) {
-
- /* CPU Configuration */
- case GT_CPU:
- s->regs[GT_CPU] = val;
- break;
- case GT_MULTI:
- /* Read-only register as only one GT64xxx is present on the CPU bus */
- break;
-
- /* CPU Address Decode */
- case GT_PCI0IOLD:
- s->regs[GT_PCI0IOLD] = val & 0x00007fff;
- s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI0M0LD:
- s->regs[GT_PCI0M0LD] = val & 0x00007fff;
- s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI0M1LD:
- s->regs[GT_PCI0M1LD] = val & 0x00007fff;
- s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI1IOLD:
- s->regs[GT_PCI1IOLD] = val & 0x00007fff;
- s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI1M0LD:
- s->regs[GT_PCI1M0LD] = val & 0x00007fff;
- s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI1M1LD:
- s->regs[GT_PCI1M1LD] = val & 0x00007fff;
- s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI0IOHD:
- case GT_PCI0M0HD:
- case GT_PCI0M1HD:
- case GT_PCI1IOHD:
- case GT_PCI1M0HD:
- case GT_PCI1M1HD:
- s->regs[saddr] = val & 0x0000007f;
- gt64120_pci_mapping(s);
- break;
- case GT_PCI0IOREMAP:
- case GT_PCI0M0REMAP:
- case GT_PCI0M1REMAP:
- case GT_PCI1IOREMAP:
- case GT_PCI1M0REMAP:
- case GT_PCI1M1REMAP:
- s->regs[saddr] = val & 0x000007ff;
- gt64120_pci_mapping(s);
- break;
-
- /* CPU Error Report */
- case GT_CPUERR_ADDRLO:
- case GT_CPUERR_ADDRHI:
- case GT_CPUERR_DATALO:
- case GT_CPUERR_DATAHI:
- case GT_CPUERR_PARITY:
- /* Read-only registers, do nothing */
- break;
-
- /* CPU Sync Barrier */
- case GT_PCI0SYNC:
- case GT_PCI1SYNC:
- /* Read-only registers, do nothing */
- break;
-
- /* ECC */
- case GT_ECC_ERRDATALO:
- case GT_ECC_ERRDATAHI:
- case GT_ECC_MEM:
- case GT_ECC_CALC:
- case GT_ECC_ERRADDR:
- /* Read-only registers, do nothing */
- break;
-
- /* PCI Internal */
- case GT_PCI0_CMD:
- case GT_PCI1_CMD:
- s->regs[saddr] = val & 0x0401fc0f;
- break;
- case GT_PCI0_CFGADDR:
- s->pci->config_reg = val & 0x80fffffc;
- break;
- case GT_PCI0_CFGDATA:
- pci_host_data_writel(s->pci, 0, val);
- break;
-
- /* SDRAM Parameters */
- case GT_SDRAM_B0:
- case GT_SDRAM_B1:
- case GT_SDRAM_B2:
- case GT_SDRAM_B3:
- /* We don't simulate electrical parameters of the SDRAM.
- Accept, but ignore the values. */
- s->regs[saddr] = val;
- break;
-
- default:
-#if 0
- printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
-#endif
- break;
- }
-}
-
-static uint32_t gt64120_readl (void *opaque,
- target_phys_addr_t addr)
-{
- GT64120State *s = opaque;
- uint32_t val;
- uint32_t saddr;
-
- val = 0;
- saddr = (addr & 0xfff) >> 2;
-
- switch (saddr) {
-
- /* CPU Configuration */
- case GT_MULTI:
- /* Only one GT64xxx is present on the CPU bus, return
- the initial value */
- val = s->regs[saddr];
- break;
-
- /* CPU Error Report */
- case GT_CPUERR_ADDRLO:
- case GT_CPUERR_ADDRHI:
- case GT_CPUERR_DATALO:
- case GT_CPUERR_DATAHI:
- case GT_CPUERR_PARITY:
- /* Emulated memory has no error, always return the initial
- values */
- val = s->regs[saddr];
- break;
-
- /* CPU Sync Barrier */
- case GT_PCI0SYNC:
- case GT_PCI1SYNC:
- /* Reading those register should empty all FIFO on the PCI
- bus, which are not emulated. The return value should be
- a random value that should be ignored. */
- val = 0xc000ffee;
- break;
-
- /* ECC */
- case GT_ECC_ERRDATALO:
- case GT_ECC_ERRDATAHI:
- case GT_ECC_MEM:
- case GT_ECC_CALC:
- case GT_ECC_ERRADDR:
- /* Emulated memory has no error, always return the initial
- values */
- val = s->regs[saddr];
- break;
-
- case GT_CPU:
- case GT_PCI0IOLD:
- case GT_PCI0M0LD:
- case GT_PCI0M1LD:
- case GT_PCI1IOLD:
- case GT_PCI1M0LD:
- case GT_PCI1M1LD:
- case GT_PCI0IOHD:
- case GT_PCI0M0HD:
- case GT_PCI0M1HD:
- case GT_PCI1IOHD:
- case GT_PCI1M0HD:
- case GT_PCI1M1HD:
- case GT_PCI0_CMD:
- case GT_PCI1_CMD:
- case GT_PCI0IOREMAP:
- case GT_PCI0M0REMAP:
- case GT_PCI0M1REMAP:
- case GT_PCI1IOREMAP:
- case GT_PCI1M0REMAP:
- case GT_PCI1M1REMAP:
- val = s->regs[saddr];
- break;
- case GT_PCI0_IACK:
- /* Read the IRQ number */
- val = pic_read_irq(isa_pic);
- break;
-
- /* SDRAM Parameters */
- case GT_SDRAM_B0:
- case GT_SDRAM_B1:
- case GT_SDRAM_B2:
- case GT_SDRAM_B3:
- /* We don't simulate electrical parameters of the SDRAM.
- Just return the last written value. */
- val = s->regs[saddr];
- break;
-
- /* PCI Internal */
- case GT_PCI0_CFGADDR:
- val = s->pci->config_reg;
- break;
- case GT_PCI0_CFGDATA:
- val = pci_host_data_readl(s->pci, 0);
- break;
-
- default:
- val = s->regs[saddr];
-#if 0
- printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
-#endif
- break;
- }
-
-#ifdef TARGET_WORDS_BIGENDIAN
- return bswap32(val);
-#else
- return val;
-#endif
-}
-
-static CPUWriteMemoryFunc *gt64120_write[] = {
- >64120_writel,
- >64120_writel,
- >64120_writel,
-};
-
-static CPUReadMemoryFunc *gt64120_read[] = {
- >64120_readl,
- >64120_readl,
- >64120_readl,
-};
-
-static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
-{
- int slot;
-
- slot = (pci_dev->devfn >> 3);
-
- switch (slot) {
- /* PIIX4 USB */
- case 10:
- return 3;
- /* AMD 79C973 Ethernet */
- case 11:
- return 0;
- /* Crystal 4281 Sound */
- case 12:
- return 0;
- /* PCI slot 1 to 4 */
- case 18 ... 21:
- return ((slot - 18) + irq_num) & 0x03;
- /* Unknown device, don't do any translation */
- default:
- return irq_num;
- }
-}
-
-extern PCIDevice *piix4_dev;
-static int pci_irq_levels[4];
-
-static void pci_gt64120_set_irq(void *pic, int irq_num, int level)
-{
- int i, pic_irq, pic_level;
-
- pci_irq_levels[irq_num] = level;
-
- /* now we change the pic irq level according to the piix irq mappings */
- /* XXX: optimize */
- pic_irq = piix4_dev->config[0x60 + irq_num];
- if (pic_irq < 16) {
- /* The pic level is the logical OR of all the PCI irqs mapped
- to it */
- pic_level = 0;
- for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[0x60 + i])
- pic_level |= pci_irq_levels[i];
- }
- pic_set_irq(pic_irq, pic_level);
- }
-}
-
-
-void gt64120_reset(void *opaque)
-{
- GT64120State *s = opaque;
-
- /* CPU Configuration */
-#ifdef TARGET_WORDS_BIGENDIAN
- s->regs[GT_CPU] = 0x00000000;
-#else
- s->regs[GT_CPU] = 0x00000800;
-#endif
- s->regs[GT_MULTI] = 0x00000000;
-
- /* CPU Address decode FIXME: not complete*/
- s->regs[GT_PCI0IOLD] = 0x00000080;
- s->regs[GT_PCI0IOHD] = 0x0000000f;
- s->regs[GT_PCI0M0LD] = 0x00000090;
- s->regs[GT_PCI0M0HD] = 0x0000001f;
- s->regs[GT_PCI0M1LD] = 0x00000790;
- s->regs[GT_PCI0M1HD] = 0x0000001f;
- s->regs[GT_PCI1IOLD] = 0x00000100;
- s->regs[GT_PCI1IOHD] = 0x0000000f;
- s->regs[GT_PCI1M0LD] = 0x00000110;
- s->regs[GT_PCI1M0HD] = 0x0000001f;
- s->regs[GT_PCI1M1LD] = 0x00000120;
- s->regs[GT_PCI1M1HD] = 0x0000002f;
- s->regs[GT_PCI0IOREMAP] = 0x00000080;
- s->regs[GT_PCI0M0REMAP] = 0x00000090;
- s->regs[GT_PCI0M1REMAP] = 0x00000790;
- s->regs[GT_PCI1IOREMAP] = 0x00000100;
- s->regs[GT_PCI1M0REMAP] = 0x00000110;
- s->regs[GT_PCI1M1REMAP] = 0x00000120;
-
- /* CPU Error Report */
- s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
- s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
- s->regs[GT_CPUERR_DATALO] = 0xffffffff;
- s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
- s->regs[GT_CPUERR_PARITY] = 0x000000ff;
-
- /* ECC */
- s->regs[GT_ECC_ERRDATALO] = 0x00000000;
- s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
- s->regs[GT_ECC_MEM] = 0x00000000;
- s->regs[GT_ECC_CALC] = 0x00000000;
- s->regs[GT_ECC_ERRADDR] = 0x00000000;
-
- /* SDRAM Parameters */
- s->regs[GT_SDRAM_B0] = 0x00000005;
- s->regs[GT_SDRAM_B1] = 0x00000005;
- s->regs[GT_SDRAM_B2] = 0x00000005;
- s->regs[GT_SDRAM_B3] = 0x00000005;
-
- /* PCI Internal FIXME: not complete*/
-#ifdef TARGET_WORDS_BIGENDIAN
- s->regs[GT_PCI0_CMD] = 0x00000000;
- s->regs[GT_PCI1_CMD] = 0x00000000;
-#else
- s->regs[GT_PCI0_CMD] = 0x00010001;
- s->regs[GT_PCI1_CMD] = 0x00010001;
-#endif
- s->regs[GT_PCI0_IACK] = 0x00000000;
- s->regs[GT_PCI1_IACK] = 0x00000000;
-
- gt64120_pci_mapping(s);
-}
-
-PCIBus *pci_gt64120_init(void *pic)
-{
- GT64120State *s;
- PCIDevice *d;
- int gt64120;
-
- s = qemu_mallocz(sizeof(GT64120State));
- s->pci = qemu_mallocz(sizeof(GT64120PCIState));
- gt64120_reset(s);
-
- s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
- pic, 144, 4);
-
- gt64120 = cpu_register_io_memory(0, gt64120_read,
- gt64120_write, s);
- cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
-
- d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
- 0, NULL, NULL);
-
- d->config[0x00] = 0xab; // vendor_id
- d->config[0x01] = 0x11;
- d->config[0x02] = 0x46; // device_id
- d->config[0x03] = 0x20;
- d->config[0x04] = 0x06;
- d->config[0x05] = 0x00;
- d->config[0x06] = 0x80;
- d->config[0x07] = 0xa2;
- d->config[0x08] = 0x10;
- d->config[0x09] = 0x00;
- d->config[0x0A] = 0x80;
- d->config[0x0B] = 0x05;
- d->config[0x0C] = 0x08;
- d->config[0x0D] = 0x40;
- d->config[0x0E] = 0x00;
- d->config[0x0F] = 0x00;
- d->config[0x17] = 0x08;
- d->config[0x1B] = 0x1c;
- d->config[0x1F] = 0x1f;
- d->config[0x23] = 0x14;
- d->config[0x27] = 0x14;
- d->config[0x3D] = 0x01;
-
- return s->pci->bus;
-}
diff --git a/qemu/hw/mips_int.c b/qemu/hw/mips_int.c
index 05fcda7..93d599f 100644
--- a/qemu/hw/mips_int.c
+++ b/qemu/hw/mips_int.c
@@ -37,42 +37,3 @@ void cpu_mips_irq_request(void *opaque, int irq, int level)
cpu_mips_update_irq(env);
}
-#include "vl.h"
-#include "cpu.h"
-
-/* Raise IRQ to CPU if necessary. It must be called every time the active
- IRQ may change */
-void cpu_mips_update_irq(CPUState *env)
-{
- if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
- (env->CP0_Status & (1 << CP0St_IE)) &&
- !(env->hflags & MIPS_HFLAG_EXL) &&
- !(env->hflags & MIPS_HFLAG_ERL) &&
- !(env->hflags & MIPS_HFLAG_DM)) {
- if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- }
- } else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
- }
-}
-
-void cpu_mips_irq_request(void *opaque, int irq, int level)
-{
- CPUState *env = first_cpu;
-
- uint32_t mask;
-
- if (irq >= 16)
- return;
-
- mask = 1 << (irq + CP0Ca_IP);
-
- if (level) {
- env->CP0_Cause |= mask;
- } else {
- env->CP0_Cause &= ~mask;
- }
- cpu_mips_update_irq(env);
-}
-
diff --git a/qemu/hw/mips_malta.c b/qemu/hw/mips_malta.c
index c9004fb..029e18e 100644
--- a/qemu/hw/mips_malta.c
+++ b/qemu/hw/mips_malta.c
@@ -588,593 +588,3 @@ QEMUMachine mips_malta_machine = {
"MIPS Malta Core LV",
mips_malta_init,
};
-/*
- * QEMU Malta board support
- *
- * Copyright (c) 2006 Aurelien Jarno
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "vl.h"
-
-#ifdef TARGET_WORDS_BIGENDIAN
-#define BIOS_FILENAME "mips_bios.bin"
-#else
-#define BIOS_FILENAME "mipsel_bios.bin"
-#endif
-
-#ifdef MIPS_HAS_MIPS64
-#define INITRD_LOAD_ADDR (int64_t)0x80800000
-#else
-#define INITRD_LOAD_ADDR (int32_t)0x80800000
-#endif
-
-#define ENVP_ADDR (int32_t)0x80002000
-#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
-
-#define ENVP_NB_ENTRIES 16
-#define ENVP_ENTRY_SIZE 256
-
-
-extern FILE *logfile;
-
-typedef struct {
- uint32_t leds;
- uint32_t brk;
- uint32_t gpout;
- uint32_t i2coe;
- uint32_t i2cout;
- uint32_t i2csel;
- CharDriverState *display;
- char display_text[9];
-} MaltaFPGAState;
-
-static PITState *pit;
-
-/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
-static void pic_irq_request(void *opaque, int level)
-{
- cpu_mips_irq_request(opaque, 2, level);
-}
-
-/* Malta FPGA */
-static void malta_fpga_update_display(void *opaque)
-{
- char leds_text[9];
- int i;
- MaltaFPGAState *s = opaque;
-
- for (i = 7 ; i >= 0 ; i--) {
- if (s->leds & (1 << i))
- leds_text[i] = '#';
- else
- leds_text[i] = ' ';
- }
- leds_text[8] = '\0';
-
- qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
- qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
-}
-
-static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
-{
- MaltaFPGAState *s = opaque;
- uint32_t val = 0;
- uint32_t saddr;
-
- saddr = (addr & 0xfffff);
-
- switch (saddr) {
-
- /* SWITCH Register */
- case 0x00200:
- val = 0x00000000; /* All switches closed */
- break;
-
- /* STATUS Register */
- case 0x00208:
-#ifdef TARGET_WORDS_BIGENDIAN
- val = 0x00000012;
-#else
- val = 0x00000010;
-#endif
- break;
-
- /* JMPRS Register */
- case 0x00210:
- val = 0x00;
- break;
-
- /* LEDBAR Register */
- case 0x00408:
- val = s->leds;
- break;
-
- /* BRKRES Register */
- case 0x00508:
- val = s->brk;
- break;
-
- /* GPOUT Register */
- case 0x00a00:
- val = s->gpout;
- break;
-
- /* XXX: implement a real I2C controller */
-
- /* GPINP Register */
- case 0x00a08:
- /* IN = OUT until a real I2C control is implemented */
- if (s->i2csel)
- val = s->i2cout;
- else
- val = 0x00;
- break;
-
- /* I2CINP Register */
- case 0x00b00:
- val = 0x00000003;
- break;
-
- /* I2COE Register */
- case 0x00b08:
- val = s->i2coe;
- break;
-
- /* I2COUT Register */
- case 0x00b10:
- val = s->i2cout;
- break;
-
- /* I2CSEL Register */
- case 0x00b18:
- val = s->i2cout;
- break;
-
- default:
-#if 0
- printf ("malta_fpga_read: Bad register offset 0x" TLSZ "\n",
- addr);
-#endif
- break;
- }
- return val;
-}
-
-static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- MaltaFPGAState *s = opaque;
- uint32_t saddr;
-
- saddr = (addr & 0xfffff);
-
- switch (saddr) {
-
- /* SWITCH Register */
- case 0x00200:
- break;
-
- /* JMPRS Register */
- case 0x00210:
- break;
-
- /* LEDBAR Register */
- /* XXX: implement a 8-LED array */
- case 0x00408:
- s->leds = val & 0xff;
- break;
-
- /* ASCIIWORD Register */
- case 0x00410:
- snprintf(s->display_text, 9, "%08X", val);
- malta_fpga_update_display(s);
- break;
-
- /* ASCIIPOS0 to ASCIIPOS7 Registers */
- case 0x00418:
- case 0x00420:
- case 0x00428:
- case 0x00430:
- case 0x00438:
- case 0x00440:
- case 0x00448:
- case 0x00450:
- s->display_text[(saddr - 0x00418) >> 3] = (char) val;
- malta_fpga_update_display(s);
- break;
-
- /* SOFTRES Register */
- case 0x00500:
- if (val == 0x42)
- qemu_system_reset_request ();
- break;
-
- /* BRKRES Register */
- case 0x00508:
- s->brk = val & 0xff;
- break;
-
- /* GPOUT Register */
- case 0x00a00:
- s->gpout = val & 0xff;
- break;
-
- /* I2COE Register */
- case 0x00b08:
- s->i2coe = val & 0x03;
- break;
-
- /* I2COUT Register */
- case 0x00b10:
- s->i2cout = val & 0x03;
- break;
-
- /* I2CSEL Register */
- case 0x00b18:
- s->i2cout = val & 0x01;
- break;
-
- default:
-#if 0
- printf ("malta_fpga_write: Bad register offset 0x" TLSZ "\n",
- addr);
-#endif
- break;
- }
-}
-
-static CPUReadMemoryFunc *malta_fpga_read[] = {
- malta_fpga_readl,
- malta_fpga_readl,
- malta_fpga_readl
-};
-
-static CPUWriteMemoryFunc *malta_fpga_write[] = {
- malta_fpga_writel,
- malta_fpga_writel,
- malta_fpga_writel
-};
-
-void malta_fpga_reset(void *opaque)
-{
- MaltaFPGAState *s = opaque;
-
- s->leds = 0x00;
- s->brk = 0x0a;
- s->gpout = 0x00;
- s->i2coe = 0x0;
- s->i2cout = 0x3;
- s->i2csel = 0x1;
-
- s->display_text[8] = '\0';
- snprintf(s->display_text, 9, " ");
- malta_fpga_update_display(s);
-}
-
-MaltaFPGAState *malta_fpga_init(target_phys_addr_t base)
-{
- MaltaFPGAState *s;
- int malta;
-
- s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
-
- malta = cpu_register_io_memory(0, malta_fpga_read,
- malta_fpga_write, s);
- cpu_register_physical_memory(base, 0x100000, malta);
-
- s->display = qemu_chr_open("vc");
- qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "+ +\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "\n");
- qemu_chr_printf(s->display, "Malta ASCII\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "+ +\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
-
- malta_fpga_reset(s);
- qemu_register_reset(malta_fpga_reset, s);
-
- return s;
-}
-
-/* Audio support */
-#ifdef HAS_AUDIO
-static void audio_init (PCIBus *pci_bus)
-{
- struct soundhw *c;
- int audio_enabled = 0;
-
- for (c = soundhw; !audio_enabled && c->name; ++c) {
- audio_enabled = c->enabled;
- }
-
- if (audio_enabled) {
- AudioState *s;
-
- s = AUD_init ();
- if (s) {
- for (c = soundhw; c->name; ++c) {
- if (c->enabled) {
- if (c->isa) {
- fprintf(stderr, "qemu: Unsupported Sound Card: %s\n", c->name);
- exit(1);
- }
- else {
- if (pci_bus) {
- c->init.init_pci (pci_bus, s);
- }
- }
- }
- }
- }
- }
-}
-#endif
-
-/* Network support */
-static void network_init (PCIBus *pci_bus)
-{
- int i;
- NICInfo *nd;
-
- for(i = 0; i < nb_nics; i++) {
- nd = &nd_table[i];
- if (!nd->model) {
- nd->model = "pcnet";
- }
- if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
- /* The malta board has a PCNet card using PCI SLOT 11 */
- pci_nic_init(pci_bus, nd, 88);
- } else {
- pci_nic_init(pci_bus, nd, -1);
- }
- }
-}
-
-/* ROM and pseudo bootloader
-
- The following code implements a very very simple bootloader. It first
- loads the registers a0 to a3 to the values expected by the OS, and
- then jump at the kernel address.
-
- The bootloader should pass the locations of the kernel arguments and
- environment variables tables. Those tables contain the 32-bit address
- of NULL terminated strings. The environment variables table should be
- terminated by a NULL address.
-
- For a simpler implementation, the number of kernel arguments is fixed
- to two (the name of the kernel and the command line), and the two
- tables are actually the same one.
-
- The registers a0 to a3 should contain the following values:
- a0 - number of kernel arguments
- a1 - 32-bit address of the kernel arguments table
- a2 - 32-bit address of the environment variables table
- a3 - RAM size in bytes
-*/
-
-static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_addr)
-{
- uint32_t *p;
-
- /* Small bootloader */
- p = (uint32_t *) (phys_ram_base + bios_offset);
- stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */
- stl_raw(p++, 0x00000000); /* nop */
-
- /* Second part of the bootloader */
- p = (uint32_t *) (phys_ram_base + bios_offset + 0x040);
- stl_raw(p++, 0x3c040000); /* lui a0, 0 */
- stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */
- stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
- stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */
- stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
- stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
- stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x00000000); /* nop */
-}
-
-static void prom_set(int index, const char *string, ...)
-{
- va_list ap;
- int32_t *p;
- int32_t table_addr;
- char *s;
-
- if (index >= ENVP_NB_ENTRIES)
- return;
-
- p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
- p += index;
-
- if (string == NULL) {
- stl_raw(p, 0);
- return;
- }
-
- table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
- s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
-
- stl_raw(p, table_addr);
-
- va_start(ap, string);
- vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
- va_end(ap);
-}
-
-/* Kernel */
-static int64_t load_kernel (CPUState *env)
-{
- int64_t kernel_addr = 0;
- int index = 0;
- long initrd_size;
-
- if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, &kernel_addr) < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
- env->kernel_filename);
- exit(1);
- }
-
- /* load initrd */
- initrd_size = 0;
- if (env->initrd_filename) {
- initrd_size = load_image(env->initrd_filename,
- phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
- if (initrd_size == (target_ulong) -1) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- env->initrd_filename);
- exit(1);
- }
- }
-
- /* Store command line. */
- prom_set(index++, env->kernel_filename);
- if (initrd_size > 0)
- prom_set(index++, "rd_start=0x" TLSZ " rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline);
- else
- prom_set(index++, env->kernel_cmdline);
-
- /* Setup minimum environment variables */
- prom_set(index++, "memsize");
- prom_set(index++, "%i", env->ram_size);
- prom_set(index++, "modetty0");
- prom_set(index++, "38400n8r");
- prom_set(index++, NULL);
-
- return kernel_addr;
-}
-
-static void main_cpu_reset(void *opaque)
-{
- CPUState *env = opaque;
- cpu_reset(env);
-
- /* The bootload does not need to be rewritten as it is located in a
- read only location. The kernel location and the arguments table
- location does not change. */
- if (env->kernel_filename)
- load_kernel (env);
-}
-
-void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename)
-{
- char buf[1024];
- unsigned long bios_offset;
- int64_t kernel_addr;
- PCIBus *pci_bus;
- CPUState *env;
- RTCState *rtc_state;
- /* fdctrl_t *floppy_controller; */
- MaltaFPGAState *malta_fpga;
- int ret;
-
- env = cpu_init();
- register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
- qemu_register_reset(main_cpu_reset, env);
-
- /* allocate RAM */
- cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
-
- /* Map the bios at two physical locations, as on the real board */
- bios_offset = ram_size + vga_ram_size;
- cpu_register_physical_memory(0x1e000000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
- cpu_register_physical_memory(0x1fc00000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
-
- /* Load a BIOS image except if a kernel image has been specified. In
- the later case, just write a small bootloader to the flash
- location. */
- if (kernel_filename) {
- env->ram_size = ram_size;
- env->kernel_filename = kernel_filename;
- env->kernel_cmdline = kernel_cmdline;
- env->initrd_filename = initrd_filename;
- kernel_addr = load_kernel(env);
- write_bootloader(env, bios_offset, kernel_addr);
- } else {
- snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
- ret = load_image(buf, phys_ram_base + bios_offset);
- if (ret != BIOS_SIZE) {
- fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
- buf);
- exit(1);
- }
- }
-
- /* Board ID = 0x420 (Malta Board with CoreLV)
- XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
- map to the board ID. */
- stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
-
- /* Init internal devices */
- cpu_mips_clock_init(env);
- cpu_mips_irqctrl_init();
-
- /* FPGA */
- malta_fpga = malta_fpga_init(0x1f000000LL);
-
- /* Interrupt controller */
- isa_pic = pic_init(pic_irq_request, env);
-
- /* Northbridge */
- pci_bus = pci_gt64120_init(isa_pic);
-
- /* Southbridge */
- piix4_init(pci_bus, 80);
- pci_piix3_ide_init(pci_bus, bs_table, 81);
- usb_uhci_init(pci_bus, 82);
- piix4_pm_init(pci_bus, 83);
- pit = pit_init(0x40, 0);
- DMA_init(0);
-
- /* Super I/O */
- kbd_init();
- rtc_state = rtc_init(0x70, 8);
- serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
- parallel_init(0x378, 7, parallel_hds[0]);
- /* XXX: The floppy controller does not work correctly, something is
- probably wrong.
- floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table); */
-
- /* Sound card */
-#ifdef HAS_AUDIO
- audio_init(pci_bus);
-#endif
-
- /* Network card */
- network_init(pci_bus);
-}
-
-QEMUMachine mips_malta_machine = {
- "malta",
- "MIPS Malta Core LV",
- mips_malta_init,
-};
diff --git a/qemu/hw/mips_timer.c b/qemu/hw/mips_timer.c
index 321e270..bc83036 100644
--- a/qemu/hw/mips_timer.c
+++ b/qemu/hw/mips_timer.c
@@ -81,86 +81,3 @@ void cpu_mips_clock_init (CPUState *env)
cpu_mips_update_count(env, 1, 0);
}
-#include "vl.h"
-
-void cpu_mips_irqctrl_init (void)
-{
-}
-
-/* XXX: do not use a global */
-uint32_t cpu_mips_get_random (CPUState *env)
-{
- static uint32_t seed = 0;
- uint32_t idx;
- seed = seed * 314159 + 1;
- idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
- return idx;
-}
-
-/* MIPS R4K timer */
-uint32_t cpu_mips_get_count (CPUState *env)
-{
- return env->CP0_Count +
- (uint32_t)muldiv64(qemu_get_clock(vm_clock),
- 100 * 1000 * 1000, ticks_per_sec);
-}
-
-static void cpu_mips_update_count (CPUState *env, uint32_t count,
- uint32_t compare)
-{
- uint64_t now, next;
- uint32_t tmp;
-
- tmp = count;
- if (count == compare)
- tmp++;
- now = qemu_get_clock(vm_clock);
- next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
- if (next == now)
- next++;
-#if 0
- if (logfile) {
- fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
- __func__, now, count, compare, next - now);
- }
-#endif
- /* Store new count and compare registers */
- env->CP0_Compare = compare;
- env->CP0_Count =
- count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
- /* Adjust timer */
- qemu_mod_timer(env->timer, next);
-}
-
-void cpu_mips_store_count (CPUState *env, uint32_t value)
-{
- cpu_mips_update_count(env, value, env->CP0_Compare);
-}
-
-void cpu_mips_store_compare (CPUState *env, uint32_t value)
-{
- cpu_mips_update_count(env, cpu_mips_get_count(env), value);
- cpu_mips_irq_request(env, 7, 0);
-}
-
-static void mips_timer_cb (void *opaque)
-{
- CPUState *env;
-
- env = opaque;
-#if 0
- if (logfile) {
- fprintf(logfile, "%s\n", __func__);
- }
-#endif
- cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
- cpu_mips_irq_request(env, 7, 1);
-}
-
-void cpu_mips_clock_init (CPUState *env)
-{
- env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
- env->CP0_Compare = 0;
- cpu_mips_update_count(env, 1, 0);
-}
-
diff --git a/qemu/hw/realview.c b/qemu/hw/realview.c
index f968e1a..ea42705 100644
--- a/qemu/hw/realview.c
+++ b/qemu/hw/realview.c
@@ -136,141 +136,3 @@ QEMUMachine realview_machine = {
"ARM RealView Emulation Baseboard (ARM926EJ-S)",
realview_init
};
-/*
- * ARM RealView Baseboard System emulation.
- *
- * Copyright (c) 2006 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licenced under the GPL.
- */
-
-#include "vl.h"
-#include "arm_pic.h"
-
-/* Board init. */
-
-static void realview_init(int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename)
-{
- CPUState *env;
- void *pic;
- void *scsi_hba;
- PCIBus *pci_bus;
- NICInfo *nd;
- int n;
- int done_smc = 0;
-
- env = cpu_init();
- cpu_arm_set_model(env, ARM_CPUID_ARM926);
- //cpu_arm_set_model(env, ARM_CPUID_ARM11MPCORE);
- /* ??? RAM shoud repeat to fill physical memory space. */
- /* SDRAM at address zero. */
- cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
-
- arm_sysctl_init(0x10000000, 0xc1400400);
- pic = arm_pic_init_cpu(env);
- /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3
- is nIRQ (there are inconsistencies). However Linux 2.6.17 expects
- GIC1 to be nIRQ and ignores all the others, so do that for now. */
- pic = arm_gic_init(0x10040000, pic, ARM_PIC_CPU_IRQ);
- pl050_init(0x10006000, pic, 20, 0);
- pl050_init(0x10007000, pic, 21, 1);
-
- pl011_init(0x10009000, pic, 12, serial_hds[0]);
- pl011_init(0x1000a000, pic, 13, serial_hds[1]);
- pl011_init(0x1000b000, pic, 14, serial_hds[2]);
- pl011_init(0x1000c000, pic, 15, serial_hds[3]);
-
- /* DMA controller is optional, apparently. */
- pl080_init(0x10030000, pic, 24, 2);
-
- sp804_init(0x10011000, pic, 4);
- sp804_init(0x10012000, pic, 5);
-
- pl110_init(ds, 0x10020000, pic, 23, 1);
-
- pci_bus = pci_vpb_init(pic, 48, 1);
- if (usb_enabled) {
- usb_ohci_init(pci_bus, 3, -1);
- }
- scsi_hba = lsi_scsi_init(pci_bus, -1);
- for (n = 0; n < MAX_DISKS; n++) {
- if (bs_table[n]) {
- lsi_scsi_attach(scsi_hba, bs_table[n], n);
- }
- }
- for(n = 0; n < nb_nics; n++) {
- nd = &nd_table[n];
- if (!nd->model)
- nd->model = done_smc ? "rtl8139" : "smc91c111";
- if (strcmp(nd->model, "smc91c111") == 0) {
- smc91c111_init(nd, 0x4e000000, pic, 28);
- } else {
- pci_nic_init(pci_bus, nd, -1);
- }
- }
-
- /* Memory map for RealView Emulation Baseboard: */
- /* 0x10000000 System registers. */
- /* 0x10001000 System controller. */
- /* 0x10002000 Two-Wire Serial Bus. */
- /* 0x10003000 Reserved. */
- /* 0x10004000 AACI. */
- /* 0x10005000 MCI. */
- /* 0x10006000 KMI0. */
- /* 0x10007000 KMI1. */
- /* 0x10008000 Character LCD. */
- /* 0x10009000 UART0. */
- /* 0x1000a000 UART1. */
- /* 0x1000b000 UART2. */
- /* 0x1000c000 UART3. */
- /* 0x1000d000 SSPI. */
- /* 0x1000e000 SCI. */
- /* 0x1000f000 Reserved. */
- /* 0x10010000 Watchdog. */
- /* 0x10011000 Timer 0+1. */
- /* 0x10012000 Timer 2+3. */
- /* 0x10013000 GPIO 0. */
- /* 0x10014000 GPIO 1. */
- /* 0x10015000 GPIO 2. */
- /* 0x10016000 Reserved. */
- /* 0x10017000 RTC. */
- /* 0x10018000 DMC. */
- /* 0x10019000 PCI controller config. */
- /* 0x10020000 CLCD. */
- /* 0x10030000 DMA Controller. */
- /* 0x10040000 GIC1 (FIQ1). */
- /* 0x10050000 GIC2 (IRQ1). */
- /* 0x10060000 GIC3 (FIQ2). */
- /* 0x10070000 GIC4 (IRQ2). */
- /* 0x10080000 SMC. */
- /* 0x40000000 NOR flash. */
- /* 0x44000000 DoC flash. */
- /* 0x48000000 SRAM. */
- /* 0x4c000000 Configuration flash. */
- /* 0x4e000000 Ethernet. */
- /* 0x4f000000 USB. */
- /* 0x50000000 PISMO. */
- /* 0x54000000 PISMO. */
- /* 0x58000000 PISMO. */
- /* 0x5c000000 PISMO. */
- /* 0x60000000 PCI. */
- /* 0x61000000 PCI Self Config. */
- /* 0x62000000 PCI Config. */
- /* 0x63000000 PCI IO. */
- /* 0x64000000 PCI mem 0. */
- /* 0x68000000 PCI mem 1. */
- /* 0x6c000000 PCI mem 2. */
-
- arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
- initrd_filename, 0x33b);
-}
-
-QEMUMachine realview_machine = {
- "realview",
- "ARM RealView Emulation Baseboard (ARM926EJ-S)",
- realview_init
-};
diff --git a/qemu/hw/sparc32_dma.c b/qemu/hw/sparc32_dma.c
index c0d5811..b17a12b 100644
--- a/qemu/hw/sparc32_dma.c
+++ b/qemu/hw/sparc32_dma.c
@@ -281,286 +281,3 @@ void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
s->esp_opaque = esp_opaque;
s->lance_opaque = lance_opaque;
}
-/*
- * QEMU Sparc32 DMA controller emulation
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include "vl.h"
-
-/* debug DMA */
-//#define DEBUG_DMA
-
-/*
- * This is the DMA controller part of chip STP2000 (Master I/O), also
- * produced as NCR89C100. See
- * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
- * and
- * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
- */
-
-#ifdef DEBUG_DMA
-#define DPRINTF(fmt, args...) \
-do { printf("DMA: " fmt , ##args); } while (0)
-#define pic_set_irq_new(ctl, irq, level) \
- do { printf("DMA: set_irq(%d): %d\n", (irq), (level)); \
- pic_set_irq_new((ctl), (irq),(level));} while (0)
-#else
-#define DPRINTF(fmt, args...)
-#endif
-
-#define DMA_REGS 8
-#define DMA_MAXADDR (DMA_REGS * 4 - 1)
-
-#define DMA_VER 0xa0000000
-#define DMA_INTR 1
-#define DMA_INTREN 0x10
-#define DMA_WRITE_MEM 0x100
-#define DMA_LOADED 0x04000000
-#define DMA_RESET 0x80
-
-typedef struct DMAState DMAState;
-
-struct DMAState {
- uint32_t dmaregs[DMA_REGS];
- int espirq, leirq;
- void *iommu, *esp_opaque, *lance_opaque, *intctl;
-};
-
-void ledma_set_irq(void *opaque, int isr)
-{
- DMAState *s = opaque;
-
- pic_set_irq_new(s->intctl, s->leirq, isr);
-}
-
-/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
- uint8_t *buf, int len, int do_bswap)
-{
- DMAState *s = opaque;
- int i;
-
- DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
- addr |= s->dmaregs[7];
- if (do_bswap) {
- sparc_iommu_memory_read(s->iommu, addr, buf, len);
- } else {
- addr &= ~1;
- len &= ~1;
- sparc_iommu_memory_read(s->iommu, addr, buf, len);
- for(i = 0; i < len; i += 2) {
- bswap16s((uint16_t *)(buf + i));
- }
- }
-}
-
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
- uint8_t *buf, int len, int do_bswap)
-{
- DMAState *s = opaque;
- int l, i;
- uint16_t tmp_buf[32];
-
- DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
- addr |= s->dmaregs[7];
- if (do_bswap) {
- sparc_iommu_memory_write(s->iommu, addr, buf, len);
- } else {
- addr &= ~1;
- len &= ~1;
- while (len > 0) {
- l = len;
- if (l > sizeof(tmp_buf))
- l = sizeof(tmp_buf);
- for(i = 0; i < l; i += 2) {
- tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
- }
- sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
- len -= l;
- buf += l;
- addr += l;
- }
- }
-}
-
-void espdma_raise_irq(void *opaque)
-{
- DMAState *s = opaque;
-
- s->dmaregs[0] |= DMA_INTR;
- pic_set_irq_new(s->intctl, s->espirq, 1);
-}
-
-void espdma_clear_irq(void *opaque)
-{
- DMAState *s = opaque;
-
- s->dmaregs[0] &= ~DMA_INTR;
- pic_set_irq_new(s->intctl, s->espirq, 0);
-}
-
-void espdma_memory_read(void *opaque, uint8_t *buf, int len)
-{
- DMAState *s = opaque;
-
- DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
- sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
- s->dmaregs[0] |= DMA_INTR;
- s->dmaregs[1] += len;
-}
-
-void espdma_memory_write(void *opaque, uint8_t *buf, int len)
-{
- DMAState *s = opaque;
-
- DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
- sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
- s->dmaregs[0] |= DMA_INTR;
- s->dmaregs[1] += len;
-}
-
-static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
-{
- DMAState *s = opaque;
- uint32_t saddr;
-
- saddr = (addr & DMA_MAXADDR) >> 2;
- DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]);
-
- return s->dmaregs[saddr];
-}
-
-static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- DMAState *s = opaque;
- uint32_t saddr;
-
- saddr = (addr & DMA_MAXADDR) >> 2;
- DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
- switch (saddr) {
- case 0:
- if (!(val & DMA_INTREN))
- pic_set_irq_new(s->intctl, s->espirq, 0);
- if (val & DMA_RESET) {
- esp_reset(s->esp_opaque);
- } else if (val & 0x40) {
- val &= ~0x40;
- } else if (val == 0)
- val = 0x40;
- val &= 0x0fffffff;
- val |= DMA_VER;
- break;
- case 1:
- s->dmaregs[0] |= DMA_LOADED;
- break;
- case 4:
- if (!(val & DMA_INTREN))
- pic_set_irq_new(s->intctl, s->leirq, 0);
- if (val & DMA_RESET)
- pcnet_h_reset(s->lance_opaque);
- val &= 0x0fffffff;
- val |= DMA_VER;
- break;
- default:
- break;
- }
- s->dmaregs[saddr] = val;
-}
-
-static CPUReadMemoryFunc *dma_mem_read[3] = {
- dma_mem_readl,
- dma_mem_readl,
- dma_mem_readl,
-};
-
-static CPUWriteMemoryFunc *dma_mem_write[3] = {
- dma_mem_writel,
- dma_mem_writel,
- dma_mem_writel,
-};
-
-static void dma_reset(void *opaque)
-{
- DMAState *s = opaque;
-
- memset(s->dmaregs, 0, DMA_REGS * 4);
- s->dmaregs[0] = DMA_VER;
- s->dmaregs[4] = DMA_VER;
-}
-
-static void dma_save(QEMUFile *f, void *opaque)
-{
- DMAState *s = opaque;
- unsigned int i;
-
- for (i = 0; i < DMA_REGS; i++)
- qemu_put_be32s(f, &s->dmaregs[i]);
-}
-
-static int dma_load(QEMUFile *f, void *opaque, int version_id)
-{
- DMAState *s = opaque;
- unsigned int i;
-
- if (version_id != 1)
- return -EINVAL;
- for (i = 0; i < DMA_REGS; i++)
- qemu_get_be32s(f, &s->dmaregs[i]);
-
- return 0;
-}
-
-void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, void *intctl)
-{
- DMAState *s;
- int dma_io_memory;
-
- s = qemu_mallocz(sizeof(DMAState));
- if (!s)
- return NULL;
-
- s->espirq = espirq;
- s->leirq = leirq;
- s->iommu = iommu;
- s->intctl = intctl;
-
- dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
- cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory);
-
- register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s);
- qemu_register_reset(dma_reset, s);
-
- return s;
-}
-
-void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
- void *lance_opaque)
-{
- DMAState *s = opaque;
-
- s->esp_opaque = esp_opaque;
- s->lance_opaque = lance_opaque;
-}
diff --git a/qemu/linux-user/m68k-semi.c b/qemu/linux-user/m68k-semi.c
index e964a6e..7f6ddda 100644
--- a/qemu/linux-user/m68k-semi.c
+++ b/qemu/linux-user/m68k-semi.c
@@ -214,219 +214,3 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
}
}
-/*
- * m68k/ColdFire Semihosting ssycall interface
- *
- * Copyright (c) 2005 CodeSourcery, LLC. Written by Paul Brook.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <sys/time.h>
-#include <time.h>
-
-#include "qemu.h"
-
-#define HOSTED_EXIT 0
-#define HOSTED_PUTCHAR 1 /* Obsolete */
-#define HOSTED_OPEN 2
-#define HOSTED_CLOSE 3
-#define HOSTED_READ 4
-#define HOSTED_WRITE 5
-#define HOSTED_LSEEK 6
-#define HOSTED_RENAME 7
-#define HOSTED_UNLINK 8
-#define HOSTED_STAT 9
-#define HOSTED_FSTAT 10
-#define HOSTED_GETTIMEOFDAY 11
-#define HOSTED_ISATTY 12
-#define HOSTED_SYSTEM 13
-
-typedef uint32_t gdb_mode_t;
-typedef uint32_t gdb_time_t;
-
-struct m68k_gdb_stat {
- uint32_t gdb_st_dev; /* device */
- uint32_t gdb_st_ino; /* inode */
- gdb_mode_t gdb_st_mode; /* protection */
- uint32_t gdb_st_nlink; /* number of hard links */
- uint32_t gdb_st_uid; /* user ID of owner */
- uint32_t gdb_st_gid; /* group ID of owner */
- uint32_t gdb_st_rdev; /* device type (if inode device) */
- uint64_t gdb_st_size; /* total size, in bytes */
- uint64_t gdb_st_blksize; /* blocksize for filesystem I/O */
- uint64_t gdb_st_blocks; /* number of blocks allocated */
- gdb_time_t gdb_st_atime; /* time of last access */
- gdb_time_t gdb_st_mtime; /* time of last modification */
- gdb_time_t gdb_st_ctime; /* time of last change */
-};
-
-struct gdb_timeval {
- gdb_time_t tv_sec; /* second */
- uint64_t tv_usec; /* microsecond */
-};
-
-#define GDB_O_RDONLY 0x0
-#define GDB_O_WRONLY 0x1
-#define GDB_O_RDWR 0x2
-#define GDB_O_APPEND 0x8
-#define GDB_O_CREAT 0x200
-#define GDB_O_TRUNC 0x400
-#define GDB_O_EXCL 0x800
-
-static int translate_openflags(int flags)
-{
- int hf;
-
- if (flags & GDB_O_WRONLY)
- hf = O_WRONLY;
- else if (flags & GDB_O_RDWR)
- hf = O_RDWR;
- else
- hf = O_RDONLY;
-
- if (flags & GDB_O_APPEND) hf |= O_APPEND;
- if (flags & GDB_O_CREAT) hf |= O_CREAT;
- if (flags & GDB_O_TRUNC) hf |= O_TRUNC;
- if (flags & GDB_O_EXCL) hf |= O_EXCL;
-
- return hf;
-}
-
-static void translate_stat(struct m68k_gdb_stat *p, struct stat *s)
-{
- p->gdb_st_dev = tswap16(s->st_dev);
- p->gdb_st_ino = tswap16(s->st_ino);
- p->gdb_st_mode = tswap32(s->st_mode);
- p->gdb_st_nlink = tswap16(s->st_nlink);
- p->gdb_st_uid = tswap16(s->st_uid);
- p->gdb_st_gid = tswap16(s->st_gid);
- p->gdb_st_rdev = tswap16(s->st_rdev);
- p->gdb_st_size = tswap32(s->st_size);
- p->gdb_st_atime = tswap32(s->st_atime);
- p->gdb_st_mtime = tswap32(s->st_mtime);
- p->gdb_st_ctime = tswap32(s->st_ctime);
- p->gdb_st_blksize = tswap32(s->st_blksize);
- p->gdb_st_blocks = tswap32(s->st_blocks);
-}
-
-static inline uint32_t check_err(CPUM68KState *env, uint32_t code)
-{
- if (code == (uint32_t)-1) {
- env->sr |= CCF_C;
- } else {
- env->sr &= ~CCF_C;
- env->dregs[0] = code;
- }
- return code;
-}
-
-#define ARG(x) tswap32(args[x])
-void do_m68k_semihosting(CPUM68KState *env, int nr)
-{
- uint32_t *args;
-
- args = (uint32_t *)env->dregs[1];
- switch (nr) {
- case HOSTED_EXIT:
- exit(env->dregs[0]);
- case HOSTED_OPEN:
- /* Assume name is NULL terminated. */
- check_err(env, open((char *)ARG(0), translate_openflags(ARG(2)),
- ARG(3)));
- break;
- case HOSTED_CLOSE:
- {
- /* Ignore attempts to close stdin/out/err. */
- int fd = ARG(0);
- if (fd > 2)
- check_err(env, close(fd));
- else
- check_err(env, 0);
- break;
- }
- case HOSTED_READ:
- check_err(env, read(ARG(0), (void *)ARG(1), ARG(2)));
- break;
- case HOSTED_WRITE:
- check_err(env, write(ARG(0), (void *)ARG(1), ARG(2)));
- break;
- case HOSTED_LSEEK:
- {
- uint64_t off;
- off = (uint32_t)ARG(2) | ((uint64_t)ARG(1) << 32);
- check_err(env, lseek(ARG(0), off, ARG(3)));
- }
- break;
- case HOSTED_RENAME:
- /* Assume names are NULL terminated. */
- check_err(env, rename((char *)ARG(0), (char *)ARG(2)));
- break;
- case HOSTED_UNLINK:
- /* Assume name is NULL terminated. */
- check_err(env, unlink((char *)ARG(0)));
- break;
- case HOSTED_STAT:
- /* Assume name is NULL terminated. */
- {
- struct stat s;
- int rc;
- rc = check_err(env, stat((char *)ARG(0), &s));
- if (rc == 0) {
- translate_stat((struct m68k_gdb_stat *)ARG(2), &s);
- }
- }
- break;
- case HOSTED_FSTAT:
- {
- struct stat s;
- int rc;
- rc = check_err(env, fstat(ARG(0), &s));
- if (rc == 0) {
- translate_stat((struct m68k_gdb_stat *)ARG(1), &s);
- }
- }
- break;
- case HOSTED_GETTIMEOFDAY:
- {
- struct timeval tv;
- struct gdb_timeval *p;
- int rc;
- rc = check_err(env, gettimeofday(&tv, NULL));
- if (rc != 0) {
- p = (struct gdb_timeval *)ARG(0);
- p->tv_sec = tswap32(tv.tv_sec);
- p->tv_usec = tswap64(tv.tv_usec);
- }
- }
- break;
- case HOSTED_ISATTY:
- check_err(env, isatty(ARG(0)));
- break;
- case HOSTED_SYSTEM:
- /* Assume name is NULL terminated. */
- check_err(env, system((char *)ARG(0)));
- break;
- default:
- cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
- }
-}
diff --git a/qemu/linux-user/m68k-sim.c b/qemu/linux-user/m68k-sim.c
index d8767e5..667808e 100644
--- a/qemu/linux-user/m68k-sim.c
+++ b/qemu/linux-user/m68k-sim.c
@@ -169,174 +169,3 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr);
}
}
-/*
- * m68k simulator syscall interface
- *
- * Copyright (c) 2005 CodeSourcery, LLC. Written by Paul Brook.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <time.h>
-
-#include "qemu.h"
-
-#define SYS_EXIT 1
-#define SYS_READ 3
-#define SYS_WRITE 4
-#define SYS_OPEN 5
-#define SYS_CLOSE 6
-#define SYS_BRK 17
-#define SYS_FSTAT 28
-#define SYS_ISATTY 29
-#define SYS_LSEEK 199
-
-struct m86k_sim_stat {
- uint16_t sim_st_dev;
- uint16_t sim_st_ino;
- uint32_t sim_st_mode;
- uint16_t sim_st_nlink;
- uint16_t sim_st_uid;
- uint16_t sim_st_gid;
- uint16_t sim_st_rdev;
- uint32_t sim_st_size;
- uint32_t sim_st_atime;
- uint32_t sim_st_mtime;
- uint32_t sim_st_ctime;
- uint32_t sim_st_blksize;
- uint32_t sim_st_blocks;
-};
-
-static inline uint32_t check_err(CPUM68KState *env, uint32_t code)
-{
- env->dregs[0] = code;
- if (code == (uint32_t)-1) {
- env->dregs[1] = errno;
- } else {
- env->dregs[1] = 0;
- }
- return code;
-}
-
-#define SIM_O_APPEND 0x0008
-#define SIM_O_CREAT 0x0200
-#define SIM_O_TRUNC 0x0400
-#define SIM_O_EXCL 0x0800
-#define SIM_O_NONBLOCK 0x4000
-#define SIM_O_NOCTTY 0x8000
-#define SIM_O_SYNC 0x2000
-
-static int translate_openflags(int flags)
-{
- int hf;
-
- switch (flags & 3) {
- case 0: hf = O_RDONLY; break;
- case 1: hf = O_WRONLY; break;
- case 2: hf = O_RDWR; break;
- default: hf = O_RDWR; break;
- }
-
- if (flags & SIM_O_APPEND) hf |= O_APPEND;
- if (flags & SIM_O_CREAT) hf |= O_CREAT;
- if (flags & SIM_O_TRUNC) hf |= O_TRUNC;
- if (flags & SIM_O_EXCL) hf |= O_EXCL;
- if (flags & SIM_O_NONBLOCK) hf |= O_NONBLOCK;
- if (flags & SIM_O_NOCTTY) hf |= O_NOCTTY;
- if (flags & SIM_O_SYNC) hf |= O_SYNC;
-
- return hf;
-}
-
-#define ARG(x) tswap32(args[x])
-void do_m68k_simcall(CPUM68KState *env, int nr)
-{
- uint32_t *args;
-
- args = (uint32_t *)(env->aregs[7] + 4);
- switch (nr) {
- case SYS_EXIT:
- exit(ARG(0));
- case SYS_READ:
- check_err(env, read(ARG(0), (void *)ARG(1), ARG(2)));
- break;
- case SYS_WRITE:
- check_err(env, write(ARG(0), (void *)ARG(1), ARG(2)));
- break;
- case SYS_OPEN:
- check_err(env, open((char *)ARG(0), translate_openflags(ARG(1)),
- ARG(2)));
- break;
- case SYS_CLOSE:
- {
- /* Ignore attempts to close stdin/out/err. */
- int fd = ARG(0);
- if (fd > 2)
- check_err(env, close(fd));
- else
- check_err(env, 0);
- break;
- }
- case SYS_BRK:
- {
- int32_t ret;
-
- ret = do_brk((void *)ARG(0));
- if (ret == -ENOMEM)
- ret = -1;
- check_err(env, ret);
- }
- break;
- case SYS_FSTAT:
- {
- struct stat s;
- int rc;
- struct m86k_sim_stat *p;
- rc = check_err(env, fstat(ARG(0), &s));
- if (rc == 0) {
- p = (struct m86k_sim_stat *)ARG(1);
- p->sim_st_dev = tswap16(s.st_dev);
- p->sim_st_ino = tswap16(s.st_ino);
- p->sim_st_mode = tswap32(s.st_mode);
- p->sim_st_nlink = tswap16(s.st_nlink);
- p->sim_st_uid = tswap16(s.st_uid);
- p->sim_st_gid = tswap16(s.st_gid);
- p->sim_st_rdev = tswap16(s.st_rdev);
- p->sim_st_size = tswap32(s.st_size);
- p->sim_st_atime = tswap32(s.st_atime);
- p->sim_st_mtime = tswap32(s.st_mtime);
- p->sim_st_ctime = tswap32(s.st_ctime);
- p->sim_st_blksize = tswap32(s.st_blksize);
- p->sim_st_blocks = tswap32(s.st_blocks);
- }
- }
- break;
- case SYS_ISATTY:
- check_err(env, isatty(ARG(0)));
- break;
- case SYS_LSEEK:
- check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
- break;
- default:
- cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr);
- }
-}
diff --git a/qemu/tests/hello-mips.c b/qemu/tests/hello-mips.c
index c0b0996..f825673 100644
--- a/qemu/tests/hello-mips.c
+++ b/qemu/tests/hello-mips.c
@@ -62,67 +62,3 @@ void __start(void)
write (1, "Hello, World!\n", 14);
exit1 (42);
}
-/*
-* MIPS o32 Linux syscall example
-*
-* http://www.linux-mips.org/wiki/RISC/os
-* http://www.linux-mips.org/wiki/MIPSABIHistory
-* http://www.linux.com/howtos/Assembly-HOWTO/mips.shtml
-*
-* mipsel-linux-gcc -nostdlib -mno-abicalls -fno-PIC -mabi=32 \
-* -O2 -static -o hello-mips hello-mips.c
-*
-*/
-#define __NR_SYSCALL_BASE 4000
-#define __NR_exit (__NR_SYSCALL_BASE+ 1)
-#define __NR_write (__NR_SYSCALL_BASE+ 4)
-
-static inline void exit1(int status)
-{
- register unsigned long __a0 asm("$4") = (unsigned long) status;
-
- __asm__ __volatile__ (
- " .set push \n"
- " .set noreorder \n"
- " li $2, %0 \n"
- " syscall \n"
- " .set pop "
- :
- : "i" (__NR_exit), "r" (__a0)
- : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
- "memory");
-}
-
-static inline int write(int fd, const char *buf, int len)
-{
- register unsigned long __a0 asm("$4") = (unsigned long) fd;
- register unsigned long __a1 asm("$5") = (unsigned long) buf;
- register unsigned long __a2 asm("$6") = (unsigned long) len;
- register unsigned long __a3 asm("$7");
- unsigned long __v0;
-
- __asm__ __volatile__ (
- " .set push \n"
- " .set noreorder \n"
- " li $2, %2 \n"
- " syscall \n"
- " move %0, $2 \n"
- " .set pop "
- : "=r" (__v0), "=r" (__a3)
- : "i" (__NR_write), "r" (__a0), "r" (__a1), "r" (__a2)
- : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
- "memory");
-
-/* if (__a3 == 0) */
- return (int) __v0;
-/*
- errno = __v0;
- return -1;
- */
-}
-
-void __start(void)
-{
- write (1, "Hello, World!\n", 14);
- exit1 (42);
-}
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_______________________________________________
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: Duplicate content in files
[not found] ` <46784C46.206-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
@ 2007-06-20 7:51 ` Avi Kivity
0 siblings, 0 replies; 6+ messages in thread
From: Avi Kivity @ 2007-06-20 7:51 UTC (permalink / raw)
To: Baruch Even; +Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Baruch Even wrote:
> Anthony Liguori wrote:
>> Baruch Even wrote:
>>> Luca wrote:
>>>
>>>> On 6/19/07, Baruch Even <baruch-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org> wrote:
>>>>
>>>>> Hello,
>>>>>
>>>>> I've tried to diff kvm-28 qemu directory with qemu 0.9.0 and I see
>>>>> that
>>>>> some files in the kvm sources have the content of the file
>>>>> duplicated,
>>>>> f.ex. qemu/hw/mips_int.c has it's own content twice in the kvm
>>>>> tree, it
>>>>> only has it once in qemu as it should be. Look for the include
>>>>> directives and you'll see what I mean.
>>
>> A patch to eliminate this stuff would be very nice!
>
> Attached.
Applied, thanks.
--
Do not meddle in the internals of kernels, for they are subtle and quick to panic.
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2007-06-20 7:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-06-19 20:34 Duplicate content in files Baruch Even
[not found] ` <46783DC8.2010006-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
2007-06-19 20:46 ` Luca
[not found] ` <68676e00706191346r615b798emd90be772ac3bdd45-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2007-06-19 20:50 ` Baruch Even
[not found] ` <46784183.4070502-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
2007-06-19 21:11 ` Anthony Liguori
[not found] ` <46784668.2060106-rdkfGonbjUSkNkDKm+mE6A@public.gmane.org>
2007-06-19 21:36 ` Baruch Even
[not found] ` <46784C46.206-6P1Dz+XQpLLYtjvyW6yDsg@public.gmane.org>
2007-06-20 7:51 ` Avi Kivity
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