From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [patch] wrong tlb flush order Date: Thu, 21 Jun 2007 11:50:09 +0300 Message-ID: <467A3BC1.4030808@qumranet.com> References: <4678F5E7.7070908@qumranet.com> <97D612E30E1F88419025B06CB4CF1BE102862D5D@scsmsx412.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel To: "Li, Xin B" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Li, Xin B wrote: >> BTW, >> >> The current VMX code does not make sense to me: >> >> static void vmx_flush_tlb(struct kvm_vcpu *vcpu) >> { >> vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3)); >> } >> >> > > The point is, vmexits will invalidate all TLB entries on Intel VT > processor today. > Yes. This was based on some text in the manual that I can't find anymore. I long suspected that it is unnecessary. -- error compiling committee.c: too many arguments to function ------------------------------------------------------------------------- This SF.net email is sponsored by DB2 Express Download DB2 Express C - the FREE version of DB2 express and take control of your XML. No limits. Just data. Click to get it now. http://sourceforge.net/powerbar/db2/