Re: In kernel PIC support: kernel patch

Gregory Haskins
2007-06-22T12:02:34Z

On Fri, 2007-06-22 at 12:46 +0300, Avi Kivity wrote:
> Gregory Haskins wrote:
> > I actually kind of like the distinction you are making between the
> > INTERRUPT, EXTINT, and ISA/IOAPIC APIs and keeping them consistent
> > across modes. As you suggested below, the ISA/IOAPIC API probably
> > should really stay as one (I vote for retaining the ISA name) since the
> > wiring is an invariant of the platform presented by qemu/bochs.
> >
> >
>
> Well, kvm shouldn't really know how the qemu hardware is wired up. It
> can change; and non-qemu userspaces should always be possible.

I agree, but we have a ways to go to get there to fully support this
notion. :( In addition to an API that supports it, any in-kernel
components will also likely need to know how to be wired up dynamically.
For instance, today the lapic branch assumes the PIC is wired to LINT0
(as decreed by QEMU), but other architectures might have it wired to an
IOAPIC pin (for routing to other CPUs besides the BSP), for instance).

I guess I was thinking the APIs would evolve as that new capability
emerged. But you are right...if we can get this part of the API correct
now, lets do it.

>
> When we change an irq line, there are three things that matter:
>
> - which chip the line is connected to (PIC 1, PIC2, IOAPIC)
> - which line we're talking about
> - what level the line is to have
>
> If we allow lists of such triplets to be sent via a single ioctl, then
> we can optimize the case where lines are wired together without teaching
> kvm about the board layout.

Sounds like a good approach.

>
> (the ISA name might annoy our non-x86 friends. I see nothing x86
> specific about the interface)
>

Good point. Lets go with the other suggestions you and Eddie are
making.

-Greg