[PATCH] lmsw sets lower 16 bits of cr0, not just lower 4

[PATCH] lmsw sets lower 16 bits of cr0, not just lower 4

[Rusty Russell]

According to my Intel manual, although lmsw only causes an exit when
trying to set the bottom 4 bits, it is supposed to set the bottom 16
bits of cr0.

Signed-off-by: Rusty Russell <rusty-8n+1lVoiYb80n/F98K4Iww@public.gmane.org>

diff -r f06a5d7dc984 drivers/kvm/kvm_main.c
--- a/drivers/kvm/kvm_main.c	Wed Jul 25 13:05:14 2007 +1000
+++ b/drivers/kvm/kvm_main.c	Wed Jul 25 13:15:24 2007 +1000
@@ -526,7 +526,7 @@ EXPORT_SYMBOL_GPL(set_cr0);
 
 void lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 {
-	set_cr0(vcpu, (vcpu->cr0 & ~0x0ful) | (msw & 0x0f));
+	set_cr0(vcpu, (vcpu->cr0 & ~0xffffUL) | (msw & 0xffff));
 }
 EXPORT_SYMBOL_GPL(lmsw);
 



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Re: [PATCH] lmsw sets lower 16 bits of cr0, not just lower 4

[Avi Kivity]

Rusty Russell wrote:
> According to my Intel manual, although lmsw only causes an exit when
> trying to set the bottom 4 bits, it is supposed to set the bottom 16
> bits of cr0.
>
>   

Well, _my_ Intel manual (2A) says:

> Loads the source operand into the machine status word, bits 0 through 
> 15 of register CR0. The
> source operand can be a 16-bit general-purpose register or a memory 
> location. Only the low-
> order 4 bits of the source operand (which contains the PE, MP, EM, and 
> TS flags) are loaded
> into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not 
> affected. The operand-
> size attribute has no effect on this instruction.


-- 
error compiling committee.c: too many arguments to function


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Re: [PATCH] lmsw sets lower 16 bits of cr0, not just lower 4

[Rusty Russell]

On Wed, 2007-08-01 at 21:44 +0300, Avi Kivity wrote:
> Rusty Russell wrote:
> > According to my Intel manual, although lmsw only causes an exit when
> > trying to set the bottom 4 bits, it is supposed to set the bottom 16
> > bits of cr0.
> >
> >   
> 
> Well, _my_ Intel manual (2A) says:
> 
> > Loads the source operand into the machine status word, bits 0 through 
> > 15 of register CR0. The
> > source operand can be a 16-bit general-purpose register or a memory 
> > location. Only the low-
> > order 4 bits of the source operand (which contains the PE, MP, EM, and 
> > TS flags) are loaded

Damn, I should have kept reading.

Sorry for the noise!
Rusty.



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