[PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

[PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

[Yang, Sheng]

[-- Attachment #1: Type: text/plain, Size: 10294 bytes --]

>From 34ee5ae67ff5d3f4b8a0b9313dd80980f57705eb Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Date: Mon, 29 Oct 2007 09:40:42 +0800
Subject: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

This patch based on CR8/TPR patch, and enable the TPR
shadow(FlexPriority)
for 32bit Windows. Since TPR is accessed very frequently by 32bit
Windows,
especially SMP guest, with FlexPriority enabled, we saw significant
performance gain.

Signed-off-by: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
 drivers/kvm/kvm.h      |    1 +
 drivers/kvm/kvm_main.c |   18 ++++++-
 drivers/kvm/vmx.c      |  113
++++++++++++++++++++++++++++++++++++++++++------
 drivers/kvm/vmx.h      |    5 ++
 4 files changed, 121 insertions(+), 16 deletions(-)

diff --git a/drivers/kvm/kvm.h b/drivers/kvm/kvm.h
index b08fc9e..31b2dd7 100644
--- a/drivers/kvm/kvm.h
+++ b/drivers/kvm/kvm.h
@@ -384,6 +384,7 @@ struct kvm {
 	struct kvm_ioapic *vioapic;
 	int round_robin_prev_vcpu;
 	unsigned int tss_addr;
+	struct page *apic_access_page;
 };
 
 static inline struct kvm_pic *pic_irqchip(struct kvm *kvm)
diff --git a/drivers/kvm/kvm_main.c b/drivers/kvm/kvm_main.c
index 9a3d663..506bebb 100644
--- a/drivers/kvm/kvm_main.c
+++ b/drivers/kvm/kvm_main.c
@@ -1293,14 +1293,21 @@ static int emulator_read_emulated(unsigned long
addr,
 		memcpy(val, vcpu->mmio_data, bytes);
 		vcpu->mmio_read_completed = 0;
 		return X86EMUL_CONTINUE;
-	} else if (emulator_read_std(addr, val, bytes, vcpu)
-		   == X86EMUL_CONTINUE)
-		return X86EMUL_CONTINUE;
+	}
 
 	gpa = vcpu->mmu.gva_to_gpa(vcpu, addr);
+
+	/* For APIC access vmexit */
+	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
+		goto mmio;
+
+	if (emulator_read_std(addr, val, bytes, vcpu)
+			== X86EMUL_CONTINUE)
+		return X86EMUL_CONTINUE;
 	if (gpa == UNMAPPED_GVA)
 		return X86EMUL_PROPAGATE_FAULT;
 
+mmio:
 	/*
 	 * Is this MMIO handled locally?
 	 */
@@ -1343,9 +1350,14 @@ static int
emulator_write_emulated_onepage(unsigned long addr,
 		return X86EMUL_PROPAGATE_FAULT;
 	}
 
+	/* For APIC access vmexit */
+	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
+		goto mmio;
+
 	if (emulator_write_phys(vcpu, gpa, val, bytes))
 		return X86EMUL_CONTINUE;
 
+mmio:
 	/*
 	 * Is this MMIO handled locally?
 	 */
diff --git a/drivers/kvm/vmx.c b/drivers/kvm/vmx.c
index f4f6fbc..42e7fad 100644
--- a/drivers/kvm/vmx.c
+++ b/drivers/kvm/vmx.c
@@ -86,6 +86,7 @@ static struct vmcs_config {
 	u32 revision_id;
 	u32 pin_based_exec_ctrl;
 	u32 cpu_based_exec_ctrl;
+	u32 cpu_based_2nd_exec_ctrl;
 	u32 vmexit_ctrl;
 	u32 vmentry_ctrl;
 } vmcs_config;
@@ -179,6 +180,29 @@ static inline int vm_need_tpr_shadow(struct kvm
*kvm)
 	return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 }
 
+static inline int cpu_has_secondary_exec_ctrls(void)
+{
+	return (vmcs_config.cpu_based_exec_ctrl &
+		CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
+}
+
+static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
+{
+	return ((cpu_has_secondary_exec_ctrls()) &&
(irqchip_in_kernel(kvm)));
+}
+
+static inline int cpu_has_vmx_virtualize_apic_accesses(void)
+{
+	return (vmcs_config.cpu_based_2nd_exec_ctrl &
+		SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
+}
+
+static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
+{
+	return ((cpu_has_vmx_virtualize_apic_accesses()) &&
+		(irqchip_in_kernel(kvm)));
+}
+
 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 {
 	int i;
@@ -916,6 +940,7 @@ static __init int setup_vmcs_config(struct
vmcs_config *vmcs_conf)
 	u32 min, opt;
 	u32 _pin_based_exec_control = 0;
 	u32 _cpu_based_exec_control = 0;
+	u32 _cpu_based_2nd_exec_control = 0;
 	u32 _vmexit_control = 0;
 	u32 _vmentry_control = 0;
 
@@ -933,11 +958,8 @@ static __init int setup_vmcs_config(struct
vmcs_config *vmcs_conf)
 	      CPU_BASED_USE_IO_BITMAPS |
 	      CPU_BASED_MOV_DR_EXITING |
 	      CPU_BASED_USE_TSC_OFFSETING;
-#ifdef CONFIG_X86_64
-	opt = CPU_BASED_TPR_SHADOW;
-#else
-	opt = 0;
-#endif
+	opt = CPU_BASED_TPR_SHADOW |
+	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 				&_cpu_based_exec_control) < 0)
 		return -EIO;
@@ -946,6 +968,18 @@ static __init int setup_vmcs_config(struct
vmcs_config *vmcs_conf)
 		_cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 					   ~CPU_BASED_CR8_STORE_EXITING;
 #endif
+	if (_cpu_based_exec_control &
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
+		min = 0;
+		opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+		if (adjust_vmx_controls(min, opt,
MSR_IA32_VMX_PROCBASED_CTLS2,
+					&_cpu_based_2nd_exec_control) <
0)
+			return -EIO;
+	}
+#ifndef CONFIG_X86_64
+	if (!(_cpu_based_2nd_exec_control &
+
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
+		_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
+#endif
 
 	min = 0;
 #ifdef CONFIG_X86_64
@@ -983,6 +1017,7 @@ static __init int setup_vmcs_config(struct
vmcs_config *vmcs_conf)
 
 	vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
 	vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
+	vmcs_conf->cpu_based_2nd_exec_ctrl =
_cpu_based_2nd_exec_control;
 	vmcs_conf->vmexit_ctrl         = _vmexit_control;
 	vmcs_conf->vmentry_ctrl        = _vmentry_control;
 
@@ -1425,6 +1460,23 @@ static void seg_setup(int seg)
 	vmcs_write32(sf->ar_bytes, 0x93);
 }
 
+static int alloc_apic_access_page(struct kvm *kvm)
+{
+	struct kvm_userspace_memory_region kvm_userspace_mem;
+	int r;
+
+	r = -EFAULT;
+	kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
+	kvm_userspace_mem.flags = 0;
+	kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
+	kvm_userspace_mem.memory_size = PAGE_SIZE;
+	r = kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
+	if (r)
+		return r;
+	kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
+	return 0;
+}
+
 /*
  * Sets up the vmcs for emulated real mode.
  */
@@ -1456,8 +1508,14 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 				CPU_BASED_CR8_LOAD_EXITING;
 #endif
 	}
+	if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
+		exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 	vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
 
+	if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
+		vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+			     vmcs_config.cpu_based_2nd_exec_ctrl);
+
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
 	vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
@@ -1526,6 +1584,10 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 	vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
 	vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
 
+	if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
+		if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
+			return -ENOMEM;
+
 	return 0;
 }
 
@@ -1614,13 +1676,17 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 
 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
 
-#ifdef CONFIG_X86_64
-	vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
-	if (vm_need_tpr_shadow(vmx->vcpu.kvm))
-		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
-			     page_to_phys(vmx->vcpu.apic->regs_page));
-	vmcs_write32(TPR_THRESHOLD, 0);
-#endif
+	if (cpu_has_vmx_tpr_shadow()) {
+		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
+		if (vm_need_tpr_shadow(vmx->vcpu.kvm))
+			vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
+
page_to_phys(vmx->vcpu.apic->regs_page));
+		vmcs_write32(TPR_THRESHOLD, 0);
+	}
+
+	if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
+		vmcs_write64(APIC_ACCESS_ADDR,
+
page_to_phys(vmx->vcpu.kvm->apic_access_page));
 
 	vmx->vcpu.cr0 = 0x60000010;
 	vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
@@ -2092,6 +2158,26 @@ static int handle_vmcall(struct kvm_vcpu *vcpu,
struct kvm_run *kvm_run)
 	return 1;
 }
 
+static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run
*kvm_run)
+{
+	u64 exit_qualification;
+	enum emulation_result er;
+	unsigned long offset;
+
+	exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
+	offset = exit_qualification & 0xffful;
+
+	er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
+
+	if (er !=  EMULATE_DONE) {
+		printk(KERN_ERR
+		       "Fail to handle apic access vmexit! Offset is
0x%lx\n",
+		       offset);
+		return -ENOTSUPP;
+	}
+	return 1;
+}
+
 /*
  * The exit handlers return 1 if the exit was handled fully and guest
execution
  * may resume.  Otherwise they set the kvm_run parameter to indicate
what needs
@@ -2111,7 +2197,8 @@ static int (*kvm_vmx_exit_handlers[])(struct
kvm_vcpu *vcpu,
 	[EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
 	[EXIT_REASON_HLT]                     = handle_halt,
 	[EXIT_REASON_VMCALL]                  = handle_vmcall,
-	[EXIT_REASON_TPR_BELOW_THRESHOLD]     =
handle_tpr_below_threshold
+	[EXIT_REASON_TPR_BELOW_THRESHOLD]     =
handle_tpr_below_threshold,
+	[EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
 };
 
 static const int kvm_vmx_max_exit_handlers =
diff --git a/drivers/kvm/vmx.h b/drivers/kvm/vmx.h
index 270d477..c84bd37 100644
--- a/drivers/kvm/vmx.h
+++ b/drivers/kvm/vmx.h
@@ -89,6 +89,8 @@ enum vmcs_field {
 	TSC_OFFSET_HIGH                 = 0x00002011,
 	VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 	VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
+	APIC_ACCESS_ADDR		= 0x00002014,
+	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
 	VMCS_LINK_POINTER               = 0x00002800,
 	VMCS_LINK_POINTER_HIGH          = 0x00002801,
 	GUEST_IA32_DEBUGCTL             = 0x00002802,
@@ -214,6 +216,7 @@ enum vmcs_field {
 #define EXIT_REASON_MSR_WRITE           32
 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
+#define EXIT_REASON_APIC_ACCESS         44
 
 /*
  * Interruption-information format
@@ -307,4 +310,6 @@ enum vmcs_field {
 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 
+#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	9
+
 #endif
-- 
1.5.2

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[-- Type: application/octet-stream, Size: 9919 bytes --]

From 34ee5ae67ff5d3f4b8a0b9313dd80980f57705eb Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@intel.com>
Date: Mon, 29 Oct 2007 09:40:42 +0800
Subject: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

This patch based on CR8/TPR patch, and enable the TPR shadow(FlexPriority)
for 32bit Windows. Since TPR is accessed very frequently by 32bit Windows,
especially SMP guest, with FlexPriority enabled, we saw significant
performance gain.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
 drivers/kvm/kvm.h      |    1 +
 drivers/kvm/kvm_main.c |   18 ++++++-
 drivers/kvm/vmx.c      |  113 ++++++++++++++++++++++++++++++++++++++++++------
 drivers/kvm/vmx.h      |    5 ++
 4 files changed, 121 insertions(+), 16 deletions(-)

diff --git a/drivers/kvm/kvm.h b/drivers/kvm/kvm.h
index b08fc9e..31b2dd7 100644
--- a/drivers/kvm/kvm.h
+++ b/drivers/kvm/kvm.h
@@ -384,6 +384,7 @@ struct kvm {
 	struct kvm_ioapic *vioapic;
 	int round_robin_prev_vcpu;
 	unsigned int tss_addr;
+	struct page *apic_access_page;
 };
 
 static inline struct kvm_pic *pic_irqchip(struct kvm *kvm)
diff --git a/drivers/kvm/kvm_main.c b/drivers/kvm/kvm_main.c
index 9a3d663..506bebb 100644
--- a/drivers/kvm/kvm_main.c
+++ b/drivers/kvm/kvm_main.c
@@ -1293,14 +1293,21 @@ static int emulator_read_emulated(unsigned long addr,
 		memcpy(val, vcpu->mmio_data, bytes);
 		vcpu->mmio_read_completed = 0;
 		return X86EMUL_CONTINUE;
-	} else if (emulator_read_std(addr, val, bytes, vcpu)
-		   == X86EMUL_CONTINUE)
-		return X86EMUL_CONTINUE;
+	}
 
 	gpa = vcpu->mmu.gva_to_gpa(vcpu, addr);
+
+	/* For APIC access vmexit */
+	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
+		goto mmio;
+
+	if (emulator_read_std(addr, val, bytes, vcpu)
+			== X86EMUL_CONTINUE)
+		return X86EMUL_CONTINUE;
 	if (gpa == UNMAPPED_GVA)
 		return X86EMUL_PROPAGATE_FAULT;
 
+mmio:
 	/*
 	 * Is this MMIO handled locally?
 	 */
@@ -1343,9 +1350,14 @@ static int emulator_write_emulated_onepage(unsigned long addr,
 		return X86EMUL_PROPAGATE_FAULT;
 	}
 
+	/* For APIC access vmexit */
+	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
+		goto mmio;
+
 	if (emulator_write_phys(vcpu, gpa, val, bytes))
 		return X86EMUL_CONTINUE;
 
+mmio:
 	/*
 	 * Is this MMIO handled locally?
 	 */
diff --git a/drivers/kvm/vmx.c b/drivers/kvm/vmx.c
index f4f6fbc..42e7fad 100644
--- a/drivers/kvm/vmx.c
+++ b/drivers/kvm/vmx.c
@@ -86,6 +86,7 @@ static struct vmcs_config {
 	u32 revision_id;
 	u32 pin_based_exec_ctrl;
 	u32 cpu_based_exec_ctrl;
+	u32 cpu_based_2nd_exec_ctrl;
 	u32 vmexit_ctrl;
 	u32 vmentry_ctrl;
 } vmcs_config;
@@ -179,6 +180,29 @@ static inline int vm_need_tpr_shadow(struct kvm *kvm)
 	return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 }
 
+static inline int cpu_has_secondary_exec_ctrls(void)
+{
+	return (vmcs_config.cpu_based_exec_ctrl &
+		CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
+}
+
+static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
+{
+	return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
+}
+
+static inline int cpu_has_vmx_virtualize_apic_accesses(void)
+{
+	return (vmcs_config.cpu_based_2nd_exec_ctrl &
+		SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
+}
+
+static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
+{
+	return ((cpu_has_vmx_virtualize_apic_accesses()) &&
+		(irqchip_in_kernel(kvm)));
+}
+
 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 {
 	int i;
@@ -916,6 +940,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 	u32 min, opt;
 	u32 _pin_based_exec_control = 0;
 	u32 _cpu_based_exec_control = 0;
+	u32 _cpu_based_2nd_exec_control = 0;
 	u32 _vmexit_control = 0;
 	u32 _vmentry_control = 0;
 
@@ -933,11 +958,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 	      CPU_BASED_USE_IO_BITMAPS |
 	      CPU_BASED_MOV_DR_EXITING |
 	      CPU_BASED_USE_TSC_OFFSETING;
-#ifdef CONFIG_X86_64
-	opt = CPU_BASED_TPR_SHADOW;
-#else
-	opt = 0;
-#endif
+	opt = CPU_BASED_TPR_SHADOW |
+	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 				&_cpu_based_exec_control) < 0)
 		return -EIO;
@@ -946,6 +968,18 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 		_cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 					   ~CPU_BASED_CR8_STORE_EXITING;
 #endif
+	if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
+		min = 0;
+		opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+		if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
+					&_cpu_based_2nd_exec_control) < 0)
+			return -EIO;
+	}
+#ifndef CONFIG_X86_64
+	if (!(_cpu_based_2nd_exec_control &
+				SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
+		_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
+#endif
 
 	min = 0;
 #ifdef CONFIG_X86_64
@@ -983,6 +1017,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 
 	vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
 	vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
+	vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
 	vmcs_conf->vmexit_ctrl         = _vmexit_control;
 	vmcs_conf->vmentry_ctrl        = _vmentry_control;
 
@@ -1425,6 +1460,23 @@ static void seg_setup(int seg)
 	vmcs_write32(sf->ar_bytes, 0x93);
 }
 
+static int alloc_apic_access_page(struct kvm *kvm)
+{
+	struct kvm_userspace_memory_region kvm_userspace_mem;
+	int r;
+
+	r = -EFAULT;
+	kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
+	kvm_userspace_mem.flags = 0;
+	kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
+	kvm_userspace_mem.memory_size = PAGE_SIZE;
+	r = kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
+	if (r)
+		return r;
+	kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
+	return 0;
+}
+
 /*
  * Sets up the vmcs for emulated real mode.
  */
@@ -1456,8 +1508,14 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 				CPU_BASED_CR8_LOAD_EXITING;
 #endif
 	}
+	if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
+		exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 	vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
 
+	if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
+		vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+			     vmcs_config.cpu_based_2nd_exec_ctrl);
+
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
 	vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
@@ -1526,6 +1584,10 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 	vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
 	vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
 
+	if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
+		if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
+			return -ENOMEM;
+
 	return 0;
 }
 
@@ -1614,13 +1676,17 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 
 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
 
-#ifdef CONFIG_X86_64
-	vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
-	if (vm_need_tpr_shadow(vmx->vcpu.kvm))
-		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
-			     page_to_phys(vmx->vcpu.apic->regs_page));
-	vmcs_write32(TPR_THRESHOLD, 0);
-#endif
+	if (cpu_has_vmx_tpr_shadow()) {
+		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
+		if (vm_need_tpr_shadow(vmx->vcpu.kvm))
+			vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
+				     page_to_phys(vmx->vcpu.apic->regs_page));
+		vmcs_write32(TPR_THRESHOLD, 0);
+	}
+
+	if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
+		vmcs_write64(APIC_ACCESS_ADDR,
+			     page_to_phys(vmx->vcpu.kvm->apic_access_page));
 
 	vmx->vcpu.cr0 = 0x60000010;
 	vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
@@ -2092,6 +2158,26 @@ static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 	return 1;
 }
 
+static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
+{
+	u64 exit_qualification;
+	enum emulation_result er;
+	unsigned long offset;
+
+	exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
+	offset = exit_qualification & 0xffful;
+
+	er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
+
+	if (er !=  EMULATE_DONE) {
+		printk(KERN_ERR
+		       "Fail to handle apic access vmexit! Offset is 0x%lx\n",
+		       offset);
+		return -ENOTSUPP;
+	}
+	return 1;
+}
+
 /*
  * The exit handlers return 1 if the exit was handled fully and guest execution
  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
@@ -2111,7 +2197,8 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
 	[EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
 	[EXIT_REASON_HLT]                     = handle_halt,
 	[EXIT_REASON_VMCALL]                  = handle_vmcall,
-	[EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold
+	[EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
+	[EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
 };
 
 static const int kvm_vmx_max_exit_handlers =
diff --git a/drivers/kvm/vmx.h b/drivers/kvm/vmx.h
index 270d477..c84bd37 100644
--- a/drivers/kvm/vmx.h
+++ b/drivers/kvm/vmx.h
@@ -89,6 +89,8 @@ enum vmcs_field {
 	TSC_OFFSET_HIGH                 = 0x00002011,
 	VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 	VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
+	APIC_ACCESS_ADDR		= 0x00002014,
+	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
 	VMCS_LINK_POINTER               = 0x00002800,
 	VMCS_LINK_POINTER_HIGH          = 0x00002801,
 	GUEST_IA32_DEBUGCTL             = 0x00002802,
@@ -214,6 +216,7 @@ enum vmcs_field {
 #define EXIT_REASON_MSR_WRITE           32
 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
+#define EXIT_REASON_APIC_ACCESS         44
 
 /*
  * Interruption-information format
@@ -307,4 +310,6 @@ enum vmcs_field {
 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 
+#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	9
+
 #endif
-- 
1.5.2


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Re: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

[Izik Eidus]

On Mon, 2007-10-29 at 12:55 +0800, Yang, Sheng wrote:
> >From 34ee5ae67ff5d3f4b8a0b9313dd80980f57705eb Mon Sep 17 00:00:00 2001
> From: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Date: Mon, 29 Oct 2007 09:40:42 +0800
> Subject: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)
> 
> This patch based on CR8/TPR patch, and enable the TPR
> shadow(FlexPriority)
> for 32bit Windows. Since TPR is accessed very frequently by 32bit
> Windows,
> especially SMP guest, with FlexPriority enabled, we saw significant
> performance gain.
patch look much better, and everything seems to be fine as i look at it.
lets wait avi to review it


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Re: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)

[Avi Kivity]

Yang, Sheng wrote:
> >From 34ee5ae67ff5d3f4b8a0b9313dd80980f57705eb Mon Sep 17 00:00:00 2001
> From: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Date: Mon, 29 Oct 2007 09:40:42 +0800
> Subject: [PATCH] KVM: VMX: Enable memory mapped TPR shadow(FlexPriority)
>
> This patch based on CR8/TPR patch, and enable the TPR
> shadow(FlexPriority)
> for 32bit Windows. Since TPR is accessed very frequently by 32bit
> Windows,
> especially SMP guest, with FlexPriority enabled, we saw significant
> performance gain.
>   

Applied, thanks.

-- 
Any sufficiently difficult bug is indistinguishable from a feature.


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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Dong, Eddie]

[-- Attachment #1: Type: text/plain, Size: 1722 bytes --]

 

>-----Original Message-----
>From: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org 
>[mailto:kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org] On Behalf Of 
>Izik Eidus
>Sent: 2007年10月29日 19:36
>To: Yang, Sheng
>Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
>Subject: Re: [kvm-devel] [PATCH] KVM: VMX: Enable memory 
>mappedTPR shadow(FlexPriority)
>
>On Mon, 2007-10-29 at 12:55 +0800, Yang, Sheng wrote:
>> >From 34ee5ae67ff5d3f4b8a0b9313dd80980f57705eb Mon Sep 17 
>00:00:00 2001
>> From: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>> Date: Mon, 29 Oct 2007 09:40:42 +0800
>> Subject: [PATCH] KVM: VMX: Enable memory mapped TPR 
>shadow(FlexPriority)
>> 
>> This patch based on CR8/TPR patch, and enable the TPR
>> shadow(FlexPriority)
>> for 32bit Windows. Since TPR is accessed very frequently by 32bit
>> Windows,
>> especially SMP guest, with FlexPriority enabled, we saw significant
>> performance gain.
>patch look much better, and everything seems to be fine as i 
>look at it.
>lets wait avi to review it
>
Ack too :-)

Basically this patch will have same functionality/result with what Avi
did for optimizing Windows. Dynamic patch works on all HWs, but
may crash the guest if guest kernel has integrity check or patch
guard. This one avoid this issue, but require new HWs :-)

I assume all comming processor will have this feature, some existing
processor also has this feature, so now we can have whole bunch of
solution: new HW will use HW features + any modern OSes;
old HWs will use dynamic patching with assumption no patch guard in guest
which is true so far.


thx,eddie


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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Avi Kivity]

[-- Attachment #1: Type: text/plain, Size: 1713 bytes --]

Dong, Eddie wrote:
>>
>>> From: Sheng Yang <sheng.yang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>>> Date: Mon, 29 Oct 2007 09:40:42 +0800
>>> Subject: [PATCH] KVM: VMX: Enable memory mapped TPR 
>>>       
>> shadow(FlexPriority)
>>     
>>> This patch based on CR8/TPR patch, and enable the TPR
>>> shadow(FlexPriority)
>>> for 32bit Windows. Since TPR is accessed very frequently by 32bit
>>> Windows,
>>> especially SMP guest, with FlexPriority enabled, we saw significant
>>> performance gain.
>>>       
>> patch look much better, and everything seems to be fine as i 
>> look at it.
>> lets wait avi to review it
>>
>>     
> Ack too :-)
>
> Basically this patch will have same functionality/result with what Avi
> did for optimizing Windows. Dynamic patch works on all HWs, but
> may crash the guest if guest kernel has integrity check or patch
> guard. This one avoid this issue, but require new HWs :-)
>
> I assume all comming processor will have this feature, some existing
> processor also has this feature, so now we can have whole bunch of
> solution: new HW will use HW features + any modern OSes;
> old HWs will use dynamic patching with assumption no patch guard in guest
> which is true so far.
>   

Yes. FlexPriority will be both faster and safer for those who have it
than my hack.

It may turn out that patching can improve performance even with
FlexPriority: we can patch the APIC EOI write to look if any interrupts
are pending, and only exit if the EOI will result in a new interrupt
being injected. But it is very possible that this will not be necessary
if we can achieve good interrupt mitigation with virtio.

-- 
Any sufficiently difficult bug is indistinguishable from a feature.



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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Dong, Eddie]

> 
> Yes. FlexPriority will be both faster and safer for those who have it
> than my hack. 
> 
> It may turn out that patching can improve performance even with
> FlexPriority: we can patch the APIC EOI write to look if any
> interrupts are pending, and only exit if the EOI will result in a new
> interrupt being injected. But it is very possible that this will not
> be necessary if we can achieve good interrupt mitigation with virtio.
> 
Mmm, I won't say so. The issues is: A guest EOI (level triggered IRQ)
need to clear remote IRR bit in IOAPIC side and resample that pin in
IOAPIC side.
This one is not easy to do in patched code.

thx,eddie

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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Avi Kivity]

Dong, Eddie wrote:
>> Yes. FlexPriority will be both faster and safer for those who have it
>> than my hack. 
>>
>> It may turn out that patching can improve performance even with
>> FlexPriority: we can patch the APIC EOI write to look if any
>> interrupts are pending, and only exit if the EOI will result in a new
>> interrupt being injected. But it is very possible that this will not
>> be necessary if we can achieve good interrupt mitigation with virtio.
>>
>>     
> Mmm, I won't say so. The issues is: A guest EOI (level triggered IRQ)
> need to clear remote IRR bit in IOAPIC side and resample that pin in
> IOAPIC side.
> This one is not easy to do in patched code.
>
>   

Hmm...

The patched code needs to answer the question "what will happen if I EOI 
this vector now"?  I think kvm can prepare the answer for that question, 
since it knows the irq is still asserted and that the mode is 
level-triggered.

Basically the kvm lapic code has to calculate the IRR for a "speculative 
EOI" and post that in the shared memory block.  If something changes 
(the IRQ line is de-asserted, for example) again it has to recalculate it.

So yes, it will not be easy.

-- 
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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Dor Laor]

Avi Kivity wrote:
> Dong, Eddie wrote:
>   
>>> Yes. FlexPriority will be both faster and safer for those who have it
>>> than my hack. 
>>>
>>> It may turn out that patching can improve performance even with
>>> FlexPriority: we can patch the APIC EOI write to look if any
>>> interrupts are pending, and only exit if the EOI will result in a new
>>> interrupt being injected. But it is very possible that this will not
>>> be necessary if we can achieve good interrupt mitigation with virtio.
>>>
>>>     
>>>       
>> Mmm, I won't say so. The issues is: A guest EOI (level triggered IRQ)
>> need to clear remote IRR bit in IOAPIC side and resample that pin in
>> IOAPIC side.
>> This one is not easy to do in patched code.
>>
>>   
>>     
>
> Hmm...
>
> The patched code needs to answer the question "what will happen if I EOI 
> this vector now"?  I think kvm can prepare the answer for that question, 
> since it knows the irq is still asserted and that the mode is 
> level-triggered.
>
> Basically the kvm lapic code has to calculate the IRR for a "speculative 
> EOI" and post that in the shared memory block.  If something changes 
> (the IRQ line is de-asserted, for example) again it has to recalculate it.
>
> So yes, it will not be easy.
>
>   
IMHO high performing devices like virtio have good irq 
coalescing/mitigation so there is no need to
optimize their path. Also even if you we had this improvement there is 
another time that passes
between the time that the irq is acked by the guest and the time that 
higher layer tasklet is scheduled and
really handles the action for that interrupt (duting this time more data 
should reach the host).
Since NAPI/virtio handles these situations also there is no need to have 
optimizations in the middle.
Regards,
Dor

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Re: [PATCH] KVM: VMX: Enable memory mappedTPR shadow(FlexPriority)

[Dong, Eddie]

> 
> Hmm...
> 
> The patched code needs to answer the question "what will
> happen if I EOI
> this vector now"?  I think kvm can prepare the answer for that
> question, since it knows the irq is still asserted and that the mode
> is level-triggered. 
> 
> Basically the kvm lapic code has to calculate the IRR for a
> "speculative EOI" and post that in the shared memory block.  If
> something changes (the IRQ line is de-asserted, for example) again it
> has to recalculate it. 

But even it is not changed, we need to clear remote IRR, otherwise,
a new IRQ won't be set for that vector.

thx,eddie

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