From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: RFC/patch portability: split kvm_vm_ioctl v3 Date: Tue, 30 Oct 2007 14:36:38 +0200 Message-ID: <47272556.1030901@qumranet.com> References: <1192192452.7630.16.camel@cotte.boeblingen.de.ibm.com><1193327325.8345.9.camel@cotte.boeblingen.de.ibm.com> <1193400099.10970.8.camel@cotte.boeblingen.de.ibm.com> <10EA09EFD8728347A513008B6B0DA77A024CEC4D@pdsmsx411.ccr.corp.intel.com> <47270F9E.5080007@qumranet.com> <10EA09EFD8728347A513008B6B0DA77A024CEC54@pdsmsx411.ccr.corp.intel.com> <47271C9B.1050804@de.ibm.com> <4727204E.6000606@qumranet.com> <47272410.9020502@de.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, carsteno-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org, "Zhang, Xiantao" , Hollis Blanchard To: carsteno-tA70FqPdS9bQT0dZR+AlfA@public.gmane.org Return-path: In-Reply-To: <47272410.9020502-tA70FqPdS9bQT0dZR+AlfA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Carsten Otte wrote: > >>> In addition, I would love to be able to specify which target CPUs >>> may receive that interrupt because our IPI equivalent comes out just >>> like a regular interrupt on just one target CPU. >>> >>> That boils down to something like this: >>> struct kvm_interrupt_data { >>> __u64 interrupt_number; >>> cpuset_t possible_target_cpus; >>> } >>> and an KVM_INJECT_INTERRUPT common ioctl for the vm to provide this. >> >> Are cpusets exported to userspace? >> >> x86 has something similar (IPI to a set of cpus) but it's handled >> 100% in the kernel these days. >> > No they are'nt. We'd need to come up with a different data structure > for that. A bitmap would do it, but what size? Expandable ones are messy. > Does IPI have an interrupt number too? No, it's a command (mmio) to the APIC, you tell it which vector you want and to which cpus you want it delivered. So you can have many IPI interrupt vectors. -- Any sufficiently difficult bug is indistinguishable from a feature. ------------------------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now >> http://get.splunk.com/