[patch] (big) real mode emulation - mov rl/rh/r

[patch] (big) real mode emulation - mov rl/rh/r

[Nitin A Kamble]

[-- Attachment #1.1.1: Type: text/plain, Size: 410 bytes --]

Hi Avi,
  Attached is the patch to implement emulation of instructions
  mov rl, imm8 (opcodes 0xb0-0xb3)
  mov rh, imm8 (opcodes 0xb4-0xb7)
  mov r, imm (opcodes0xb8-0xbf)

please apply.
-- 
Thanks & Regards,
Nitin
Open Source Technology Center, Intel Corporation
-----------------------------------------------------------------
The mind is like a parachute; it works much better when it's open

[-- Attachment #1.1.2: 0004-Implement-emulation-of-instructions-mov-rl-rh-r.patch --]
[-- Type: application/mbox, Size: 2232 bytes --]

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 314 bytes --]

-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/

[-- Attachment #3: Type: text/plain, Size: 186 bytes --]

_______________________________________________
kvm-devel mailing list
kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
https://lists.sourceforge.net/lists/listinfo/kvm-devel

Re: [patch] (big) real mode emulation - mov rl/rh/r

[Avi Kivity]

Nitin A Kamble wrote:
> Hi Avi,
>   Attached is the patch to implement emulation of instructions
>   mov rl, imm8 (opcodes 0xb0-0xb3)
>   mov rh, imm8 (opcodes 0xb4-0xb7)
>   mov r, imm (opcodes0xb8-0xbf)
>
>   
> @@ -146,8 +146,12 @@ static u16 opcode_table[256] = {
>         0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>         ByteOp | ImplicitOps, ImplicitOps,
> -       /* 0xB0 - 0xBF */
> -       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +       /* 0xB0 - 0xB7 */
> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov | 
> SrcImmByte,
> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov | 
> SrcImmByte,
> +       /* 0xB8 - 0xBF */
> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
>         /* 0xC0 - 0xC7 */

Perhaps adding DstReg would reduce the decoding code later on?

-- 
Any sufficiently difficult bug is indistinguishable from a feature.


-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/

Re: [patch] (big) real mode emulation - mov rl/rh/r

[Nitin A Kamble]

[-- Attachment #1.1: Type: text/plain, Size: 1878 bytes --]

On Tue, 2007-10-30 at 18:06 -0700, Avi Kivity wrote:
> Nitin A Kamble wrote:
> > Hi Avi,
> >   Attached is the patch to implement emulation of instructions
> >   mov rl, imm8 (opcodes 0xb0-0xb3)
> >   mov rh, imm8 (opcodes 0xb4-0xb7)
> >   mov r, imm (opcodes0xb8-0xbf)
> >
> >  
> > @@ -146,8 +146,12 @@ static u16 opcode_table[256] = {
> >         0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
> >         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
> >         ByteOp | ImplicitOps, ImplicitOps,
> > -       /* 0xB0 - 0xBF */
> > -       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> > +       /* 0xB0 - 0xB7 */
> > +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
> > SrcImmByte,
> > +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
> > SrcImmByte,
> > +       /* 0xB8 - 0xBF */
> > +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
> > +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
> >         /* 0xC0 - 0xC7 */
> 
> Perhaps adding DstReg would reduce the decoding code later on?

Avi,
The decoding of register is significantly different for these
instructions. It will be just moving code from one place to other place.

+               c->dst.ptr =
+                       (unsigned long *)&c->regs[VCPU_REGS_RAX + (c->b
& 0x3)];
+               c->dst.ptr =
+                       ((void *)&c->regs[VCPU_REGS_RAX + (c->b & 0x3)]
+ 1);
+               c->dst.ptr =
+                       (unsigned long *)&c->regs[VCPU_REGS_RAX + (c->b
& 0x7)];
> --
> Any sufficiently difficult bug is indistinguishable from a feature.
> 
> 
-- 
Thanks & Regards,
Nitin
Open Source Technology Center, Intel Corporation
-----------------------------------------------------------------
The mind is like a parachute; it works much better when it's open

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 314 bytes --]

-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/

[-- Attachment #3: Type: text/plain, Size: 186 bytes --]

_______________________________________________
kvm-devel mailing list
kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
https://lists.sourceforge.net/lists/listinfo/kvm-devel

Re: [patch] (big) real mode emulation - mov rl/rh/r

[Avi Kivity]

Nitin A Kamble wrote:
> On Tue, 2007-10-30 at 18:06 -0700, Avi Kivity wrote:
>   
>> Nitin A Kamble wrote:
>>     
>>> Hi Avi,
>>>   Attached is the patch to implement emulation of instructions
>>>   mov rl, imm8 (opcodes 0xb0-0xb3)
>>>   mov rh, imm8 (opcodes 0xb4-0xb7)
>>>   mov r, imm (opcodes0xb8-0xbf)
>>>
>>>  
>>> @@ -146,8 +146,12 @@ static u16 opcode_table[256] = {
>>>         0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>>>         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>>>         ByteOp | ImplicitOps, ImplicitOps,
>>> -       /* 0xB0 - 0xBF */
>>> -       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>>> +       /* 0xB0 - 0xB7 */
>>> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
>>> SrcImmByte,
>>> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
>>> SrcImmByte,
>>> +       /* 0xB8 - 0xBF */
>>> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
>>> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
>>>         /* 0xC0 - 0xC7 */
>>>       
>> Perhaps adding DstReg would reduce the decoding code later on?
>>     
>
> Avi,
> The decoding of register is significantly different for these
> instructions. It will be just moving code from one place to other place.
>
>   

Right.

But perhaps we can have a ShortReg modifier to make the decoding 
common.  There are several instructions which can use this (inc, dec, 
xchg, push, mov).

I'll look into this.

-- 
Any sufficiently difficult bug is indistinguishable from a feature.


-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/

Re: [patch] (big) real mode emulation - mov rl/rh/r

[Avi Kivity]

Avi Kivity wrote:
> Nitin A Kamble wrote:
>> On Tue, 2007-10-30 at 18:06 -0700, Avi Kivity wrote:
>>  
>>> Nitin A Kamble wrote:
>>>    
>>>> Hi Avi,
>>>>   Attached is the patch to implement emulation of instructions
>>>>   mov rl, imm8 (opcodes 0xb0-0xb3)
>>>>   mov rh, imm8 (opcodes 0xb4-0xb7)
>>>>   mov r, imm (opcodes0xb8-0xbf)
>>>>
>>>>  
>>>> @@ -146,8 +146,12 @@ static u16 opcode_table[256] = {
>>>>         0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>>>>         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
>>>>         ByteOp | ImplicitOps, ImplicitOps,
>>>> -       /* 0xB0 - 0xBF */
>>>> -       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>>>> +       /* 0xB0 - 0xB7 */
>>>> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
>>>> SrcImmByte,
>>>> +       Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
>>>> SrcImmByte,
>>>> +       /* 0xB8 - 0xBF */
>>>> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
>>>> +       Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
>>>>         /* 0xC0 - 0xC7 */
>>>>       
>>> Perhaps adding DstReg would reduce the decoding code later on?
>>>     
>>
>> Avi,
>> The decoding of register is significantly different for these
>> instructions. It will be just moving code from one place to other place.
>>
>>   
>
> Right.
>
> But perhaps we can have a ShortReg modifier to make the decoding 
> common.  There are several instructions which can use this (inc, dec, 
> xchg, push, mov).
>
> I'll look into this.
>

I've committed a few patches which enable this.  Now, a DstReg or SrcReg 
without ModRM will decode the opcode byte to get the register.  It also 
fixes a minor issue with ignoring rex prefixes on 64-bit byte insns. 
mov, inc, dec, push, and pop have been converted.

Please review these patches carefully as I haven't been able to give 
them a real workout other than booting a few guests.

-- 
Any sufficiently difficult bug is indistinguishable from a feature.


-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/