From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Markus Rechberger" Subject: Re: [PATCH] discard MSR writes Date: Tue, 20 Nov 2007 13:31:40 +0100 Message-ID: <4742D3AC.2030108@amd.com> References: <4741DF15.20708@amd.com> <200711201539.31712.amit.shah@qumranet.com> <4742B313.4080704@qumranet.com> <200711201602.43331.amit.shah@qumranet.com> <4742B88F.8000404@qumranet.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, Joerg.Roedel-5C7GfCeVMHo@public.gmane.org To: "Avi Kivity" Return-path: In-Reply-To: <4742B88F.8000404-atKUWr5tajBWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Avi Kivity wrote: > Amit Shah wrote: >> On Tuesday 20 November 2007 15:42:35 Avi Kivity wrote: >> >>> Amit Shah wrote: >>> >>>> On Tuesday 20 November 2007 15:17:54 Avi Kivity wrote: >>>> >>>>> Amit Shah wrote: >>>>> >>>>>> On Tuesday 20 November 2007 00:38:05 Markus Rechberger wrote: >>>>>> >>>>>>> this patch discards MSR writes to the Performance Event-Select >>>>>>> Registers, this is the first issue why vista seems to fail although >>>>>>> now vista ends up in an endless loop a bit later. >>>>>>> Qemu currently also discards those writes. >>>>>>> >>>>>> Won't this make the corresponding rdmsrs fail? What happens when the >>>>>> rdmsr returns an error, but windows then uses some garbage value >>>>>> (as it >>>>>> thinks the wrmsr succeeded, so the rdmsr also should)? >>>>>> >>>>> rdmsr will inject #GP for these msrs. Implementing set_msr() doesn't >>>>> affect rdmsr. >>>>> >>>>> >>>> >From the AMD programming manual, vol 2: >>>> >>>> The performance event-select registers can be read and written only by >>>> system software running at CPL = 0 using the RDMSR and WRMSR >>>> instructions, respectively. Any attempt to read or write these >>>> registers >>>> at CPL > 0 causes a general-protection exception to occur. >>>> >>> Look through the code that implements rdmsr, it doesn't care about the >>> manuals and will happily inject a #GP for rdmsr of any unimplemented >>> msr >>> (like PerfEvtSel) wrmsr and rdmsr implementations are not linked. >>> >> >> That's right; but isn't that wrong if we cause it? I mean if we just >> allow the wrmsr access to go through (and if they're actually used, >> not disabled as you mentioned separately), then there'll be no >> interrupts when the guest expects them to occur, or the rdmsr will >> fail, when the guest thinks it shouldn't have. >> >> > > It is wrong; but at least it fails loudly. We can't implement all > msrs (Intel and AMD are adding them faster than we can code), so we > must make sure that where we don't implement things, at least we have > visibility if the guest tries to use them. > >> I guess we're putting forth the same point: if the wrmsr is not for >> disabling interrupts, we shouldn't let it go through, or just >> implement the required emulation. >> > > Yes. Ignoring an msr will "fix" one guest but kill another. > I also discussed this with Joerg, since Qemu doesn't handle those MSR writes at the moment we think it's ok temporary. Lateron it should be emulated (but we're hunting a different issue at the moment). Our perfmon guys would also prefer a proper emulation. Markus ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2005. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/