From: Paolo Bonzini <pbonzini@redhat.com>
To: Xiaoyao Li <xiaoyao.li@linux.intel.com>
Cc: "Kyle Huey" <khuey@kylehuey.com>, "Chao Gao" <chao.gao@intel.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] kvm/x86/vmx: switch MSR_MISC_FEATURES_ENABLES between host and guest
Date: Thu, 14 Mar 2019 15:44:39 +0100 [thread overview]
Message-ID: <476deae9-05ca-5f3d-2178-66333674b57d@redhat.com> (raw)
In-Reply-To: <c73c2709a925b0ca08ec9fad0a0ca97e9ba15944.camel@linux.intel.com>
On 14/03/19 13:37, Xiaoyao Li wrote:
>> Adding a RDMSR for this to each vmentry is too heavy. Since we emulate
>> MSR_MISC_FEATURES_ENABLES, you can just clear the MSR on vcpu_load and
>> restore it on vcpu_put.
> One question here. Just clear the MSR on vcpu_load instead of writing the
> emulated value to MSR?
>
> I think writing the emulated value to MSR is better. As I mentioned in case 3,
> if hardware has cpuid faulting feature. Using hardware capability is more
> efficient than emulation that the emulation solution needs VM exit to inject
> #GP.
You can do that too, yes. You can add it to vmx_msr_index and it will
be handled like that.
However, that wouldn't work on AMD (which doesn't use the
kvm_define_shared_msr infrastructure) and also on hosts that don't have
MSR_MISC_FEATURES_ENABLES, so my suggestion is to add this optimization
as a separate patch.
Paolo
prev parent reply other threads:[~2019-03-14 14:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-14 6:38 [PATCH] kvm/x86/vmx: switch MSR_MISC_FEATURES_ENABLES between host and guest Xiaoyao Li
2019-03-14 7:06 ` Xiaoyao Li
2019-03-14 8:43 ` Kyle Huey
2019-03-14 10:43 ` Xiaoyao Li
2019-03-14 11:30 ` Paolo Bonzini
2019-03-14 11:28 ` Paolo Bonzini
2019-03-14 12:10 ` Xiaoyao Li
2019-03-14 12:37 ` Xiaoyao Li
2019-03-14 14:44 ` Paolo Bonzini [this message]
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