Re: [RFC] fix VMX TSC synchronicity

[Alexander Graf <alex-r27SGEef+tmzQB+pC5nmwQ@public.gmane.org>]

Avi Kivity wrote:
> Marcelo Tosatti wrote:
>   
>> Hi Avi,
>>
>> On Sun, Jan 13, 2008 at 02:19:29PM +0200, Avi Kivity wrote:
>>   
>>     
>>> Marcelo Tosatti wrote:
>>>     
>>>       
>>>> The boot TSC sync check is failing on recent Linux SMP guests on TSC
>>>> stable hosts.
>>>>
>>>>  
>>>>       
>>>>         
>>> What about tsc unstable hosts?  If your patch convinces the guest its 
>>> tsc is table, while the host tsc is not, then it may cause confusion 
>>> later on.
>>>     
>>>       
>> The adjustment to zero won't fool the guest because it assumes that the
>> TSC's are synchronized. It will simply set the guest TSC to zero on all
>> VCPUs based on the time VCPU0 was initialized.
>>
>> That is, setting -(vcpu[0].first_tsc) on all VCPU's will not correct any
>> synchronization problem.
>>
>>   
>>     
>
> What I mean is, right now we present really broken tscs to the guest.  
> After your patch, we present less-broken tscs (at boot, they will 
> closely resemble stable tscs).  But after the machine idles a bit and 
> cpufreq takes over, the tscs won't be stable any more.
>
>   

Why would the TSC break due to cpufreq? This patchset was against VMX,
which is only available on current Intel CPUs. All of those guarantee a
constant TSC increase at the maximum frequency.

Also see the Intel Documentation:

Vol. 3 18-37

For Pentium 4 processors, Intel Xeon processors (family [0FH], models
[03H and higher]); for Intel Core Solo and Intel Core Duo processors
(family [06H], model [0EH]); for the Intel Xeon processor 5100 series
and Intel Core 2 Duo processors (family [06H], model [0FH]): the
time-stamp counter increments at a constant rate. That rate may be set
by the maximum core-clock to bus-clock ratio of the processor or may be
set by the maximum resolved frequency at which the processor is booted.
The maximum resolved frequency may differ from the maximum qualified
frequency of the processor, see Section 18.17.5 for more
detail.
The specific processor configuration determines the behavior. Constant
TSC behavior ensures that the duration of each clock tick is uniform and
supports the use of the TSC as a wall clock timer even if the processor
core changes frequency.
This is the architectural behavior moving forward.

Alex


-------------------------------------------------------------------------
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/