From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [RFC] fix VMX TSC synchronicity Date: Tue, 15 Jan 2008 17:42:31 +0100 Message-ID: <478CE277.9010109@csgraf.de> References: <20080111204933.GA28318@dmt> <478A01D1.7000402@qumranet.com> <20080114160647.GA15919@dmt> <478CC448.1030901@qumranet.com> <478CC819.3040106@csgraf.de> <478CCCA9.2080300@qumranet.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Marcelo Tosatti , Alexander Graf , kvm-devel To: Avi Kivity Return-path: In-Reply-To: <478CCCA9.2080300-atKUWr5tajBWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Avi Kivity wrote: > Alexander Graf wrote: > >>>> >>>> >>>> >>>> >>> What I mean is, right now we present really broken tscs to the guest. >>> After your patch, we present less-broken tscs (at boot, they will >>> closely resemble stable tscs). But after the machine idles a bit and >>> cpufreq takes over, the tscs won't be stable any more. >>> >>> >>> >>> >> Why would the TSC break due to cpufreq? This patchset was against VMX, >> which is only available on current Intel CPUs. All of those guarantee a >> constant TSC increase at the maximum frequency. >> >> Also see the Intel Documentation: >> >> Vol. 3 18-37 >> >> For Pentium 4 processors, Intel Xeon processors (family [0FH], models >> [03H and higher]); for Intel Core Solo and Intel Core Duo processors >> (family [06H], model [0EH]); for the Intel Xeon processor 5100 series >> and Intel Core 2 Duo processors (family [06H], model [0FH]): the >> time-stamp counter increments at a constant rate. That rate may be set >> by the maximum core-clock to bus-clock ratio of the processor or may be >> set by the maximum resolved frequency at which the processor is booted. >> The maximum resolved frequency may differ from the maximum qualified >> frequency of the processor, see Section 18.17.5 for more >> detail. >> The specific processor configuration determines the behavior. Constant >> TSC behavior ensures that the duration of each clock tick is uniform and >> supports the use of the TSC as a wall clock timer even if the processor >> core changes frequency. >> This is the architectural behavior moving forward. >> > > Thanks; that's reassuring to know that it will work (at least on Intel). > > If I remember correctly, there was a statement on LKML by AMD which said that the TSC is completely broken on AMD systems, so you should not use it there anyway. ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/