Re: [PATCH 8/8] SVM: add support for Nested Paging

Avi Kivity
2008-01-27T10:24:35Z

Joerg Roedel wrote:
>> On the other hand, we want to trap cr0 so the guest can't control the
>> cache disable bits. Also cr4.pce and cr4.mce.
>>
>
> Is it a problem when the guest disables caching? It disables it only in
> its own context because it has its own copy of cr0.

Some Intel processors have a mode where cache coherency is no longer
preserved, and we need to prevent that. However from my reading of the
AMD manuals, cache coherency is preserved even with caching disabled, so
no real issue with disabling the cache.

> Cr4.pce can be
> accessible for the guests because there is no way for them to access the
> performance counter MSRs.

Yes. This was a red herring, cr0.pce only affects userspace rdpmc.

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