From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anthony Liguori Subject: Re: [Qemu-devel] [PATCH 1/5] PCI DMA API (v3) Date: Wed, 16 Apr 2008 14:54:20 -0500 Message-ID: <4806596C.4090107@us.ibm.com> References: <1208297491-1287-1-git-send-email-aliguori@us.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel@lists.sourceforge.net, Marcelo Tosatti , qemu-devel@nongnu.org, Aurelien Jarno , Paul Brook To: Blue Swirl Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces@lists.sourceforge.net Errors-To: kvm-devel-bounces@lists.sourceforge.net List-Id: kvm.vger.kernel.org Blue Swirl wrote: > On 4/16/08, Anthony Liguori wrote: > >> This patch introduces a DMA API and plumbs support through the DMA layer. We >> use a mostly opaque structure, IOVector to represent a scatter/gather list of >> physical memory. Associated with each IOVector is a read/write function and >> an opaque pointer. This allows arbitrary transformation/mapping of the >> data while providing an easy mechanism to short-cut the zero-copy case >> in the block/net backends. >> > > This looks much better also for Sparc uses. I converted pcnet to use > the IOVectors (see patch), it does not work yet but looks doable. > Excellent! > IMHO the read/write functions should be a property of the bus so that > they are hidden from the device, for pcnet it does not matter as we > have to do the swapping anyway. > For an IOMMU that has a per-device mapping, the read/write functions have to operate on a per-device basis. Regards, Anthony Liguori ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone