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* [PATCH] SVM: remove selective CR0 comment
@ 2008-04-16 15:01 Joerg Roedel
  2008-04-18 16:08 ` Avi Kivity
  0 siblings, 1 reply; 2+ messages in thread
From: Joerg Roedel @ 2008-04-16 15:01 UTC (permalink / raw)
  To: Avi Kivity; +Cc: kvm-devel, Joerg Roedel

There is not selective cr0 intercept bug. The code in the comment sets the
CR0.PG bit. But KVM sets the CR4.PG bit for SVM always to implement the paged
real mode. So the 'mov %eax,%cr0' instruction does not change the CR0.PG bit.
Selective CR0 intercepts only occur when a bit is actually changed. So its the
right behavior that there is no intercept on this instruction.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c |   11 -----------
 1 files changed, 0 insertions(+), 11 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 3379e13..55b5076 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -514,17 +514,6 @@ static void init_vmcb(struct vcpu_svm *svm)
 	control->intercept = 	(1ULL << INTERCEPT_INTR) |
 				(1ULL << INTERCEPT_NMI) |
 				(1ULL << INTERCEPT_SMI) |
-		/*
-		 * selective cr0 intercept bug?
-		 *    	0:   0f 22 d8                mov    %eax,%cr3
-		 *	3:   0f 20 c0                mov    %cr0,%eax
-		 *	6:   0d 00 00 00 80          or     $0x80000000,%eax
-		 *	b:   0f 22 c0                mov    %eax,%cr0
-		 * set cr3 ->interception
-		 * get cr0 ->interception
-		 * set cr0 -> no interception
-		 */
-		/*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 				(1ULL << INTERCEPT_CPUID) |
 				(1ULL << INTERCEPT_INVD) |
 				(1ULL << INTERCEPT_HLT) |
-- 
1.5.3.7



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^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] SVM: remove selective CR0 comment
  2008-04-16 15:01 [PATCH] SVM: remove selective CR0 comment Joerg Roedel
@ 2008-04-18 16:08 ` Avi Kivity
  0 siblings, 0 replies; 2+ messages in thread
From: Avi Kivity @ 2008-04-18 16:08 UTC (permalink / raw)
  To: Joerg Roedel; +Cc: kvm-devel

Joerg Roedel wrote:
> There is not selective cr0 intercept bug. The code in the comment sets the
> CR0.PG bit. But KVM sets the CR4.PG bit for SVM always to implement the paged
> real mode. So the 'mov %eax,%cr0' instruction does not change the CR0.PG bit.
> Selective CR0 intercepts only occur when a bit is actually changed. So its the
> right behavior that there is no intercept on this instruction.
>
>   
Applied, thanks.


-- 
Any sufficiently difficult bug is indistinguishable from a feature.


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^ permalink raw reply	[flat|nested] 2+ messages in thread

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