From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [patch 3/4] QEMU/KVM: non-virtualized ACPI PMTimer support Date: Mon, 26 May 2008 11:16:07 +0300 Message-ID: <483A71C7.2060303@qumranet.com> References: <20080524234342.983197667@localhost.localdomain> <20080525000036.645310064@localhost.localdomain> <48393D06.2060406@qumranet.com> <20080525163221.GC16012@dmt> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Chris Wright , kvm-devel To: Marcelo Tosatti Return-path: Received: from il.qumranet.com ([212.179.150.194]:26116 "EHLO il.qumranet.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752592AbYEZIQK (ORCPT ); Mon, 26 May 2008 04:16:10 -0400 In-Reply-To: <20080525163221.GC16012@dmt> Sender: kvm-owner@vger.kernel.org List-ID: Marcelo Tosatti wrote: > On Sun, May 25, 2008 at 01:18:46PM +0300, Avi Kivity wrote: > >>> int acpi_enabled; >>> -uint32_t pm_io_base, smb_io_base; >>> +uint32_t pm_io_base, pmtmr_base, smb_io_base; >>> int pm_sci_int; >>> unsigned long bios_table_cur_addr; >>> unsigned long bios_table_end_addr; >>> @@ -819,6 +819,12 @@ static void pci_bios_init_device(PCIDevi >>> pci_config_writeb(d, PCI_INTERRUPT_LINE, 9); >>> >>> pm_io_base = PM_IO_BASE; >>> + pmtmr_base = cmos_readb(0x60); >>> + pmtmr_base |= cmos_readb(0x61) << 8; >>> + pmtmr_base |= cmos_readb(0x62) << 16; >>> + pmtmr_base |= cmos_readb(0x63) << 24; >>> + if (!pmtmr_base) >>> + pmtmr_base = pm_io_base + 0x08; >>> >>> >> You're splitting the ACPI ioport range into two. I think the correct >> fix here is to have qemu supply a PMBA hint to the BIOS. If the hint is >> placing other pio resources there. >> > > What is PMBA? > > Power Management Base Address, which must equal the value of pm_io_base above. > From my understand ACPI supports an address for each register block, and > the PMTimer resides in a separate block. So what is the problem with > having different ACPI blocks in different ports? > The particular chipset we emulate has all blocks in one contiguous region starting at the PMBA. > Note that the GPE0 registers are in a different port range than > PM1EVT/PM1CNT/PMTimer already. > > That's sucky. piix4 supports GPIO pins, we should have emulated them instead of inventing our own. -- error compiling committee.c: too many arguments to function