From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [RFC]RE: [PATCH] kvm-ia64 irq assignment 1/2 kernel Date: Thu, 12 Jun 2008 15:34:10 +0300 Message-ID: <485117C2.3050009@qumranet.com> References: <51CFAB8CB6883745AE7B93B3E084EBE201CC875F@pdsmsx412.ccr.corp.intel.com> <484996EE.8060600@qumranet.com> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A14@pdsmsx412.ccr.corp.intel.com> <64146E7D-9E1E-4ED2-9682-14C05E1A9B0E@suse.de> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A61@pdsmsx412.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Alexander Graf , Jes Sorensen , kvm@vger.kernel.org, kvm-ia64@vger.kernel.org To: "Xu, Anthony" Return-path: Received: from il.qumranet.com ([212.179.150.194]:42650 "EHLO il.qumranet.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752842AbYFLMgS (ORCPT ); Thu, 12 Jun 2008 08:36:18 -0400 In-Reply-To: <51CFAB8CB6883745AE7B93B3E084EBE201CC8A61@pdsmsx412.ccr.corp.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: Xu, Anthony wrote: > Thanks for comments > > Basically we are on the same page, while I didn't find your patch about > irq assignment, can you post it in this thread again, thx? > Below patch makes all PCI devices use level-trigger , active low > interrupt, it worked well when running linux guest, I didn't try windows > guest yet. > (didn't have windows image in hand) > > Please comment! > > If this is acceptabled, we can figure out how to use IOAPIC in kvm/ia32 > based on this. Which will reduce irq sharing dramatically. > > > Thanks, > Anthony > > > > diff --git a/bios/acpi-dsdt.dsl b/bios/acpi-dsdt.dsl > index 21fc76a..4b5e824 100755 > --- a/bios/acpi-dsdt.dsl > +++ b/bios/acpi-dsdt.dsl > @@ -974,7 +974,7 @@ DefinitionBlock ( > Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link > Name(_UID, 1) > Name(_PRS, ResourceTemplate(){ > - Interrupt (, Level, ActiveHigh, Shared) > + Interrupt (, Level, ActiveLow, Shared) > { 5, 10, 11 } > I think this will fail for guests which use the PIC, since the PIC is always active high. For x86 the interrupts will have to be active high since that's how piix works. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.