RE: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

Zhang, Xiantao
2008-09-01T02:06:12Z

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Avi Kivity wrote:
> Zhang, Xiantao wrote:
>> Avi Kivity wrote:
>>
>>> Zhang, Xiantao wrote:
>>>
>>>> From 6039f279745733c52b291ec45c69eca028567c62 Mon Sep 17 00:00:00
>>>> 2001 From: Xiantao Zhang <xiantao.zhang@intel.com>
>>>> Date: Sun, 31 Aug 2008 14:27:23 +0800
>>>> Subject: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.
>>>>
>>>> The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
>>>> and doesn't have re-configure mechanism, so use 0x1f40 as default
>>>> value to support kvm/ia64's power management.
>>>> Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> ---
>>>> qemu/hw/acpi.c | 4 +++- 1 files changed, 3 insertions(+), 1
>>>> deletions(-)
>>>>
>>>> diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
>>>> index 74535bc..4fc1d3f 100644
>>>> --- a/qemu/hw/acpi.c
>>>> +++ b/qemu/hw/acpi.c
>>>> @@ -498,7 +498,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn,
>>>> uint32_t smb_io_base, pci_conf[0x0e] = 0x00; // header_type
>>>> pci_conf[0x3d] = 0x01; // interrupt pin 1
>>>>
>>>> - pci_conf[0x40] = 0x01; /* PM io base read only bit */
>>>> + pci_conf[0x40] = 0x41; /* PM io base read only bit */ +
>>>> pci_conf[0x41] = 0x1f; + pm_write_config(s, 0x80, 0x01, 1);
>>>> /*Set default pm_io_base 0x1f40*/
>>>>
>>>>
>>> Please limit this to ia64; no need to change x86 behaviour.
>>>
>>
>> X86 will do update and set pm_io_base to 0xb000 in bios, so x86
>> behaviour doesn't change with this defaul set.
>
> It still changes how x86 works. Since we want to push this to upsteam
> qemu eventually, we need to keep x86 operating in the same way as real
> hardware.
>
> (it would be even better to have ia64 firmware program this; how does
> real ia64 hardware work?)

Maybe we can limit it in ia64 side. Program firmware maybe hard to get
check-in, since Xen also share this firmware.

>From 3893e60105bc9a493c67faed760edd0a14bfed2b Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <xiantao.zhang@intel.com>
Date: Mon, 1 Sep 2008 09:47:25 +0800
Subject: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
and doesn't have re-configure mechanism, so use 0x1f40 as default value
to
support kvm/ia64's power management.
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
qemu/hw/acpi.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
index 74535bc..d12a43e 100644
--- a/qemu/hw/acpi.c
+++ b/qemu/hw/acpi.c
@@ -499,7 +499,11 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn,
uint32_t smb_io_base,
pci_conf[0x3d] = 0x01; // interrupt pin 1

pci_conf[0x40] = 0x01; /* PM io base read only bit */
-
+#if defined(TARGET_IA64)
+ pci_conf[0x40] = 0x41; /* PM io base read only bit */
+ pci_conf[0x41] = 0x1f;
+ pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base
0x1f40*/
+#endif
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);

--
1.5.1

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From 3893e60105bc9a493c67faed760edd0a14bfed2b Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <xiantao.zhang@intel.com>
Date: Mon, 1 Sep 2008 09:47:25 +0800
Subject: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
and doesn't have re-configure mechanism, so use 0x1f40 as default value to
support kvm/ia64's power management.
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
qemu/hw/acpi.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
index 74535bc..d12a43e 100644
--- a/qemu/hw/acpi.c
+++ b/qemu/hw/acpi.c
@@ -499,7 +499,11 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
pci_conf[0x3d] = 0x01; // interrupt pin 1

pci_conf[0x40] = 0x01; /* PM io base read only bit */
-
+#if defined(TARGET_IA64)
+ pci_conf[0x40] = 0x41; /* PM io base read only bit */
+ pci_conf[0x41] = 0x1f;
+ pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
+#endif
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);

--
1.5.1