[PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

Zhang, Xiantao
2008-08-31T08:02:58Z

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>From 6039f279745733c52b291ec45c69eca028567c62 Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <xiantao.zhang@intel.com>
Date: Sun, 31 Aug 2008 14:27:23 +0800
Subject: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
and doesn't have re-configure mechanism, so use 0x1f40 as default value
to
support kvm/ia64's power management.
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
qemu/hw/acpi.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
index 74535bc..4fc1d3f 100644
--- a/qemu/hw/acpi.c
+++ b/qemu/hw/acpi.c
@@ -498,7 +498,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn,
uint32_t smb_io_base,
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x01; // interrupt pin 1

- pci_conf[0x40] = 0x01; /* PM io base read only bit */
+ pci_conf[0x40] = 0x41; /* PM io base read only bit */
+ pci_conf[0x41] = 0x1f;
+ pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base
0x1f40*/

register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
--
1.5.1

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From 6039f279745733c52b291ec45c69eca028567c62 Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <xiantao.zhang@intel.com>
Date: Sun, 31 Aug 2008 14:27:23 +0800
Subject: [PATCH] KVM: Qemu: Set default pm_io_base to 0x1f40.

The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
and doesn't have re-configure mechanism, so use 0x1f40 as default value to
support kvm/ia64's power management.
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
qemu/hw/acpi.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
index 74535bc..4fc1d3f 100644
--- a/qemu/hw/acpi.c
+++ b/qemu/hw/acpi.c
@@ -498,7 +498,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x01; // interrupt pin 1

- pci_conf[0x40] = 0x01; /* PM io base read only bit */
+ pci_conf[0x40] = 0x41; /* PM io base read only bit */
+ pci_conf[0x41] = 0x1f;
+ pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/

register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
--
1.5.1