From: Avi Kivity <avi@redhat.com>
To: "Yang, Sheng" <sheng.yang@intel.com>
Cc: kvm@vger.kernel.org, Alex Williamson <alex.williamson@hp.com>
Subject: Re: [PATCH 4/4] kvm: bios: switch MTRRs to cover only the PCI range and default to WB
Date: Sat, 27 Sep 2008 16:36:01 +0300 [thread overview]
Message-ID: <48DE36C1.4070700@redhat.com> (raw)
In-Reply-To: <200809271335.10166.sheng.yang@intel.com>
Yang, Sheng wrote:
> I think we should do a little more than just write msr to update mtrr.
>
> Intel SDM 10.11.8 "MTRR consideration in MP Systems" define the procedure to
> modify MTRR msr in MP. Especially, step 4 enter no-fill cache mode(set CR0.CD
> bit and clean NW bit), step 12 re-enabled the caching(clear this two bits).
>
> We based on these behaviors to detect MTRR update.
>
>
Why not simply flush the mmu on an mtrr write?
(though of course I have no objection to doing what the manual says)
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
next prev parent reply other threads:[~2008-09-27 13:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-25 17:52 [PATCH 4/4] kvm: bios: switch MTRRs to cover only the PCI range and default to WB Alex Williamson
2008-09-27 5:35 ` Yang, Sheng
2008-09-27 13:36 ` Avi Kivity [this message]
2008-09-27 13:55 ` Zwane Mwaikambo
2008-09-28 1:58 ` Sheng Yang
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