From mboxrd@z Thu Jan 1 00:00:00 1970 From: Beth Kon Subject: [PATCH] hpet config mask fix Date: Wed, 14 Jan 2009 09:45:36 -0500 Message-ID: <496DFA90.8050100@us.ibm.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------090907000003000102090807" To: qemu-devel , kvm Return-path: Received: from e2.ny.us.ibm.com ([32.97.182.142]:58275 "EHLO e2.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761205AbZANOph (ORCPT ); Wed, 14 Jan 2009 09:45:37 -0500 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by e2.ny.us.ibm.com (8.13.1/8.13.1) with ESMTP id n0EEiCCi006970 for ; Wed, 14 Jan 2009 09:44:12 -0500 Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id n0EEjagl168818 for ; Wed, 14 Jan 2009 09:45:36 -0500 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n0EEjau8025191 for ; Wed, 14 Jan 2009 09:45:36 -0500 Sender: kvm-owner@vger.kernel.org List-ID: This is a multi-part message in MIME format. --------------090907000003000102090807 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit I discovered a bug in the hpet code that caused Windows to boot without hpet. The config mask I was using was preventing the guest from placing the hpet into 32 bit mode. --------------090907000003000102090807 Content-Type: text/x-diff; name="hpet_mask_fix.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="hpet_mask_fix.patch" diff --git a/qemu/hw/hpet.c b/qemu/hw/hpet.c index 5c1aca2..7df2d05 100644 --- a/qemu/hw/hpet.c +++ b/qemu/hw/hpet.c @@ -388,7 +388,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, switch ((addr - 0x100) % 0x20) { case HPET_TN_CFG: dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n"); - timer->config = hpet_fixup_reg(new_val, old_val, 0x3e4e); + timer->config = hpet_fixup_reg(new_val, old_val, + HPET_TN_CFG_WRITE_MASK); if (new_val & HPET_TN_32BIT) { timer->cmp = (uint32_t)timer->cmp; timer->period = (uint32_t)timer->period; @@ -456,7 +457,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, case HPET_ID: return; case HPET_CFG: - s->config = hpet_fixup_reg(new_val, old_val, 0x3); + s->config = hpet_fixup_reg(new_val, old_val, + HPET_CFG_WRITE_MASK); if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { /* Enable main counter and interrupt generation. */ s->hpet_offset = ticks_to_ns(s->hpet_counter) diff --git a/qemu/hw/hpet_emul.h b/qemu/hw/hpet_emul.h index fbe7a44..60893b6 100644 --- a/qemu/hw/hpet_emul.h +++ b/qemu/hw/hpet_emul.h @@ -36,6 +36,7 @@ #define HPET_TN_CFG 0x000 #define HPET_TN_CMP 0x008 #define HPET_TN_ROUTE 0x010 +#define HPET_CFG_WRITE_MASK 0x3 #define HPET_TN_ENABLE 0x004 @@ -45,6 +46,7 @@ #define HPET_TN_SETVAL 0x040 #define HPET_TN_32BIT 0x100 #define HPET_TN_INT_ROUTE_MASK 0x3e00 +#define HPET_TN_CFG_WRITE_MASK 0x3f4e #define HPET_TN_INT_ROUTE_SHIFT 9 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U --------------090907000003000102090807--