From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Zhao, Yu" Subject: Re: Re: KVM PCI device assignment issues Date: Tue, 24 Feb 2009 17:20:10 +0800 Message-ID: <49A3BBCA.50000@intel.com> References: <1234542767.23746.81.camel@blaa> <20090213173628.GC16841@parisc-linux.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Mark McLoughlin , kvm , "linux-pci@vger.kernel.org" , Chris Wright , "Dugger, Donald D" , "Kay, Allen M" To: Matthew Wilcox Return-path: Received: from mga01.intel.com ([192.55.52.88]:42471 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753421AbZBXJUs (ORCPT ); Tue, 24 Feb 2009 04:20:48 -0500 In-Reply-To: <20090213173628.GC16841@parisc-linux.org> Sender: kvm-owner@vger.kernel.org List-ID: Matthew Wilcox wrote: > On Fri, Feb 13, 2009 at 04:32:47PM +0000, Mark McLoughlin wrote: >> - Secondary Bus Reset (SBR) allows software to trigger a reset on = all >> devices (and functions) behind a PCI bridge. >> >> - A PCI Power Management D-state transition (D3hot to D0) can be u= sed >> to reset a device (all functions). >=20 > That's not guaranteed according to PCI PM 1.2: >=20 > 5.4.1. Software Accessible D3 (D3hot) >=20 > When programmed to D0, the function may return to the D0 Initialize= d > or D0 Uninitialized state without PCI RST# being asserted. This opt= ion > is determined at design time and allows designs the option of eithe= r > performing an internal reset or not performing an internal reset. The No_Soft_Reset bit in the PMCSR indicates which option is chosen at=20 design time: Section 3.2.4. says: Value at Reset: Device specific Read/Write: Read Only When set (=931=94), this bit indicates that devices transitioning from = D3hot=20 to D0 because of PowerState commands do not perform an internal reset.=20 Configuration Context is preserved. Upon transition from the D3hot to=20 the D0 Initialized state, no additional operating system intervention i= s=20 required to preserve Configuration Context beyond writing the PowerStat= e=20 bits. When clear (=930=94), devices do perform an internal reset upon=20 transitioning from D3hot to D0 via software control of the PowerState=20 bits. Configuration Context is lost when performing the soft reset. Upo= n=20 transition from the D3hot to the D0 state, full reinitialization=20 sequence is needed to return the device to D0 Initialized. Regardless o= f=20 this bit, devices that transition from D3hot to D0 by a system or bus=20 segment reset will return to the device state D0 Uninitialized with onl= y=20 PME context preserved if PME is supported and enabled. So the reset is guaranteed if the bit is 0. And I checked the devices on my machine, all of them who have PM perfor= m=20 internal reset when transiting from D3hot to D0 (GeForce 7300, Myri-10G= ,=20 E1000 82567, ICH10 SATA, EHCI, etc.)