From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [PATCH] KVM: Qemu: Flush i-cache after ide-dma operation in IA64 Date: Thu, 02 Apr 2009 18:53:14 +0300 Message-ID: <49D4DF6A.7080108@redhat.com> References: <10C63FAD690C13458F0B32BCED571F140F98ED4B@pdsmsx502.ccr.corp.intel.com> <49D47D7F.2040904@redhat.com> <1238686878.49d4dc9e051aa@imp.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: "Zhang, Yang" , "kvm-ia64@vger.kernel.org" , "kvm@vger.kernel.org" , "Zhang, Xiantao" To: tgingold@free.fr Return-path: Received: from mx2.redhat.com ([66.187.237.31]:41759 "EHLO mx2.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760506AbZDBPxa (ORCPT ); Thu, 2 Apr 2009 11:53:30 -0400 In-Reply-To: <1238686878.49d4dc9e051aa@imp.free.fr> Sender: kvm-owner@vger.kernel.org List-ID: tgingold@free.fr wrote: > >> What about smp? >> > > fc will broadcast to the coherence domain the cache invalidation. So it is > SMP-ready for usual machines. > > Interesting. >> I'm surprised the guest doesn't do this by itself? >> > > It doesn't had to do it. The PCI transaction will automatically invalidate > caches - but qemu doesn't emulate this (and doesn't need to do on x86). > So any DMA on ia64 will flush the instruction caches?! -- error compiling committee.c: too many arguments to function