From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anthony Liguori <aliguori@us.ibm.com>
Subject: Re: [RFC -v3 1/2] QEMU-KVM: MCE: Add MCE simulation to qemu/tcg
Date: Fri, 08 May 2009 16:08:07 -0500
Message-ID: <4A049F37.3040603@us.ibm.com>
References: <1241419677.8815.42.camel@yhuang-dev.sh.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Content-Transfer-Encoding: 7bit
Cc: Avi Kivity <avi@redhat.com>,
	Anthony Liguori <anthony@codemonkey.ws>,
	Andi Kleen <andi@firstfloor.org>, qemu-devel@nongnu.org,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
To: Huang Ying <ying.huang@intel.com>
Return-path: <kvm-owner@vger.kernel.org>
Received: from e32.co.us.ibm.com ([32.97.110.150]:57462 "EHLO
	e32.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S1754823AbZEHVIK (ORCPT <rfc822;kvm@vger.kernel.org>);
	Fri, 8 May 2009 17:08:10 -0400
Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106])
	by e32.co.us.ibm.com (8.13.1/8.13.1) with ESMTP id n48L4rnA009585
	for <kvm@vger.kernel.org>; Fri, 8 May 2009 15:04:53 -0600
Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168])
	by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n48L8APH100058
	for <kvm@vger.kernel.org>; Fri, 8 May 2009 15:08:10 -0600
Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1])
	by d03av02.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n48L89Cm011616
	for <kvm@vger.kernel.org>; Fri, 8 May 2009 15:08:10 -0600
In-Reply-To: <1241419677.8815.42.camel@yhuang-dev.sh.intel.com>
Sender: kvm-owner@vger.kernel.org
List-ID: <kvm.vger.kernel.org>

Huang Ying wrote:
> - MCE features are initialized when VCPU is intialized according to CPUID.
> - A monitor command "mce" is added to inject a MCE.
> - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
>
> Signed-off-by: Huang Ying <ying.huang@intel.com>
>
> ---
>  cpu-all.h               |    4 ++
>  cpu-exec.c              |    4 ++
>  monitor.c               |   49 +++++++++++++++++++++++++++++++++
>  target-i386/cpu.h       |   22 +++++++++++++++
>  target-i386/helper.c    |   70 ++++++++++++++++++++++++++++++++++++++++++++++++
>  target-i386/op_helper.c |   34 +++++++++++++++++++++++
>  6 files changed, 183 insertions(+)
>
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -202,6 +202,7 @@
>  #define CR4_DE_MASK   (1 << 3)
>  #define CR4_PSE_MASK  (1 << 4)
>  #define CR4_PAE_MASK  (1 << 5)
> +#define CR4_MCE_MASK  (1 << 6)
>  #define CR4_PGE_MASK  (1 << 7)
>  #define CR4_PCE_MASK  (1 << 8)
>  #define CR4_OSFXSR_SHIFT 9
> @@ -248,6 +249,17 @@
>  #define PG_ERROR_RSVD_MASK 0x08
>  #define PG_ERROR_I_D_MASK  0x10
>  
> +#define MCE_CAP_DEF	0x100
> +#define MCE_BANKS_DEF	4
> +
> +#define MCG_CTL_P	(1UL<<8)
> +
> +#define MCG_STATUS_MCIP	(1UL<<2)
> +
> +#define MCI_STATUS_VAL	(1UL<<63)
> +#define MCI_STATUS_OVER	(1UL<<62)
> +#define MCI_STATUS_UC	(1UL<<61)
> +
>  #define MSR_IA32_TSC                    0x10
>  #define MSR_IA32_APICBASE               0x1b
>  #define MSR_IA32_APICBASE_BSP           (1<<8)
> @@ -288,6 +300,11 @@
>  
>  #define MSR_MTRRdefType			0x2ff
>  
> +#define MSR_MC0_CTL			0x400
> +#define MSR_MC0_STATUS			0x401
> +#define MSR_MC0_ADDR			0x402
> +#define MSR_MC0_MISC			0x403
> +
>  #define MSR_EFER                        0xc0000080
>  
>  #define MSR_EFER_SCE   (1 << 0)
> @@ -674,6 +691,11 @@ typedef struct CPUX86State {
>         user */
>      struct APICState *apic_state;
>      uint32_t mp_state;
> +
> +    uint64 mcg_cap;
> +    uint64 mcg_status;
> +    uint64 mcg_ctl;
> +    uint64 *mce_banks;
>  } CPUX86State;
>
>   

Doesn't this need to be added to the savevm/loadvm state?

-- 
Regards,

Anthony Liguori