[PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

[PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

[Andre Przywara]

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM
does not handle the needed MSR, the injected #GP will panic the Linux
kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux
boot with an AMD K8 family guest CPU.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/svm.c |    1 -
 arch/x86/kvm/x86.c |    8 ++++++++
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 9b37043..610bcae 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -2139,7 +2139,6 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
 		break;
 	case MSR_VM_CR:
 	case MSR_VM_IGNNE:
-	case MSR_K7_HWCR:
 		pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
 		break;
 	default:
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 5a66bb9..c5a0d37 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -796,6 +796,14 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 	case MSR_EFER:
 		set_efer(vcpu, data);
 		break;
+	case MSR_K7_HWCR:
+		data &= ~0x40U;		/* ignore flush filter disable */
+		if (data != 0) {
+			pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
+				data);
+			return 1;
+		}
+		break;
 	case MSR_IA32_DEBUGCTLMSR:
 		if (!data) {
 			/* We support the non-activated case already */
-- 
1.6.1.3

[PATCH 2/4] ignore reads from AMDs C1E enabled MSR

[Andre Przywara]

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and
higher), it will access a certain MSR on every attempt to go to halt.
Explicitly handle this read and return 0 to let KVM run a Linux guest
with the native AMD host CPU propagated to the guest.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/x86.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index c5a0d37..a148f4c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1001,6 +1001,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_P6_EVNTSEL0:
 	case MSR_P6_EVNTSEL1:
 	case MSR_K7_EVNTSEL0:
+	case MSR_K8_INT_PENDING_MSG:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
-- 
1.6.1.3

[PATCH 3/4] ignore PCI ECS I/O enablement

[Andre Przywara]

Linux guests will try to enable access to the extended PCI config space
via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?)
don't use ECS, simply ignore this write attempt.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/x86.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index a148f4c..e6e61ee 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -804,6 +804,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 			return 1;
 		}
 		break;
+	case MSR_AMD64_NB_CFG:
+		break;
 	case MSR_IA32_DEBUGCTLMSR:
 		if (!data) {
 			/* We support the non-activated case already */
-- 
1.6.1.3

[PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

[Andre Przywara]

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/x86.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index e6e61ee..6ad0f93 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 		0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
 		0 /* Reserved, DCA */ | F(XMM4_1) |
 		F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
-		0 /* Reserved, XSAVE, OSXSAVE */;
+		0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR);
 	/* cpuid 0x80000001.ecx */
 	const u32 kvm_supported_word6_x86_features =
 		F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
-- 
1.6.1.3

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

[Avi Kivity]

On 06/24/2009 01:44 PM, Andre Przywara wrote:
> Signed-off-by: Andre Przywara<andre.przywara@amd.com>
> ---
>   arch/x86/kvm/x86.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index e6e61ee..6ad0f93 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
>   		0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
>   		0 /* Reserved, DCA */ | F(XMM4_1) |
>   		F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
> -		0 /* Reserved, XSAVE, OSXSAVE */;
> +		0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR);
>    

I think this should be handled in qemu, since it isn't really a cpu bit.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 3/4] ignore PCI ECS I/O enablement

[Avi Kivity]

On 06/24/2009 01:44 PM, Andre Przywara wrote:
> Linux guests will try to enable access to the extended PCI config space
> via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?)
> don't use ECS, simply ignore this write attempt.
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index a148f4c..e6e61ee 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -804,6 +804,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
>   			return 1;
>   		}
>   		break;
> +	case MSR_AMD64_NB_CFG:
> +		break;
>   	case MSR_IA32_DEBUGCTLMSR:
>   		if (!data) {
>   			/* We support the non-activated case already */
>    


I see Linux does both rdmsr and wrmsr, don't we need to support both?

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

[Avi Kivity]

On 06/24/2009 01:44 PM, Andre Przywara wrote:
> Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM
> does not handle the needed MSR, the injected #GP will panic the Linux
> kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux
> boot with an AMD K8 family guest CPU.
>
>    

Applied first two patched, thanks.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

[Andre Przywara]

Avi Kivity wrote:
> On 06/24/2009 01:44 PM, Andre Przywara wrote:
>> Signed-off-by: Andre Przywara<andre.przywara@amd.com>
>> ---
>>   arch/x86/kvm/x86.c |    2 +-
>>   1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index e6e61ee..6ad0f93 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 
>> *entry, u32 function,
>>           0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
>>           0 /* Reserved, DCA */ | F(XMM4_1) |
>>           F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
>> -        0 /* Reserved, XSAVE, OSXSAVE */;
>> +        0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR);
>>    
> 
> I think this should be handled in qemu, since it isn't really a cpu bit.

But this would require to make an exception for turning this bit on 
again after it has been trimmed.
I just made (QEMU) patches for make this trimming really work (and 
removing all the hacked bits), so I would like to not spoil this again 
by introducing another excecption. After all this is more a list of what 
KVM does _not_ support (should we make this a negative one? gets ugly 
with the reserved bits), so I would like to leave it here.
I will send out the patches to qemu-devel when I found the last bug.

Regards,
Andre.

-- 
Andre Przywara
AMD-OSRC (Dresden)
Tel: x29712

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

[Andre Przywara]

Andre Przywara wrote:
> Avi Kivity wrote:
>>> --- a/arch/x86/kvm/x86.c
>>> +++ b/arch/x86/kvm/x86.c
>>> @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct 
>>> -        0 /* Reserved, XSAVE, OSXSAVE */;
>>> +        0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR);
>>
>> I think this should be handled in qemu, since it isn't really a cpu bit.
> 
> But this would require to make an exception for turning this bit on 
> again after it has been trimmed.
> I just made (QEMU) patches for make this trimming really work (and 
> removing all the hacked bits), so I would like to not spoil this again 
> by introducing another exception.
I kind of tricked myself here. Since the hypervisor bit is (well, 
mostly) not set in the host, it will always be removed from the guest. 
So we need an exception for this anyway.
So please drop this patch, I will come up with some QEMU solution for this.

Regards,
Andre.

> After all this is more a list of what 
> KVM does _not_ support (should we make this a negative one? gets ugly 
> with the reserved bits), so I would like to leave it here.
> I will send out the patches to qemu-devel when I found the last bug.
> 

-- 
Andre Przywara
AMD-OSRC (Dresden)
Tel: x29712

[PATCH 3/4] ignore PCI ECS I/O enablement

[Andre Przywara]

Linux guests will try to enable access to the extended PCI config space
via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?)
don't use ECS, simply ignore write and read attempts.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/x86.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index a148f4c..c717037 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -804,6 +804,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 			return 1;
 		}
 		break;
+	case MSR_AMD64_NB_CFG:
+		break;
 	case MSR_IA32_DEBUGCTLMSR:
 		if (!data) {
 			/* We support the non-activated case already */
@@ -1002,6 +1004,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_P6_EVNTSEL1:
 	case MSR_K7_EVNTSEL0:
 	case MSR_K8_INT_PENDING_MSG:
+	case MSR_AMD64_NB_CFG:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
-- 
1.6.1.3

Re: [PATCH 3/4] ignore PCI ECS I/O enablement

[Avi Kivity]

On 06/24/2009 04:37 PM, Andre Przywara wrote:
> Linux guests will try to enable access to the extended PCI config space
> via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?)
> don't use ECS, simply ignore write and read attempts.
>    

Applied, thanks.

-- 
error compiling committee.c: too many arguments to function