From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jan Kiszka <jan.kiszka@web.de>
Subject: Re: [PATCH] KVM: VMX: Update instruction length on intercepted BP
Date: Sun, 14 Feb 2010 14:29:19 +0100
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References: <4B767160.4070609@web.de> <20100214075303.GF2511@redhat.com> <4B77CFD7.9080504@web.de> <20100214103445.GH2511@redhat.com> <4B77EC14.4000302@redhat.com> <4B77EF0D.4050303@web.de> <20100214124343.GK2511@redhat.com> <4B77F0EB.1050702@redhat.com> <4B77F94E.5030103@web.de>
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Cc: Gleb Natapov <gleb@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	kvm <kvm@vger.kernel.org>
To: Avi Kivity <avi@redhat.com>
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Jan Kiszka wrote:
> Avi Kivity wrote:
>> On 02/14/2010 02:43 PM, Gleb Natapov wrote:
>>>> Nice.
>>>>
>>>> [ /me goes updating his manual - September 07... ]
>>>>
>>>>     =20
>>> I can't find nothing newer then that. What is the link?
>>>   =20
>> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_875_7044=
,00.html
>>
>=20
> For the records, it's
>=20
> http://developer.amd.com/documentation/guides/Pages/default.aspx
>=20
> and then
>=20
> http://support.amd.com/us/Processor_TechDocs/24593.pdf
>=20
> (Your link still points to the previous revision.)
>=20
> nRIP is actually useless for our problem. Either SVM has built-in magic=

> to push the RIP after the INT3 on the stack or we need a workaround. I
> bet on the latter as our use case may not have been exercised that ofte=
n
> before (if at all).
>=20

On the other hand:

"Injecting an exception (TYPE =3D 3) with vectors 3 or 4 behaves like a
trap raised by INT3 and INTO instructions, respectively, in which case
the processor checks the DPL of the IDT descriptor before dispatching to
the handler."

Which /might/ also be read that not only the privilege checks are
applied, but also the original trap characteristics. And that case I
would send kudos to AMD. Will test tomorrow.

Jan


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