Re: [PATCH v2] KVM: IOAPIC: only access APIC registers one dword at a time

Avi Kivity
2010-07-05T07:54:20Z

On 07/05/2010 06:47 AM, Xiao Guangrong wrote:
>
> Avi Kivity wrote:
>
>> On 07/02/2010 11:00 AM, Xiao Guangrong wrote:
>>
>>> The IOAPIC spec says:
>>>
>>> When accessing these registers, accesses must be done one dword at a
>>> time.
>>> For example, software should never access byte 2 from the Data
>>> register before
>>> accessing bytes 0 and 1. The hardware will not attempt to recover from
>>> a bad
>>> programming model in this case.
>>>
>>> So, this patch removes other width access
>>>
>>>
>>>
>> The ioapic code also implements the ia64 iosapic. I'm guessing that
>> does support 64-bit accesses. Please check the iosapic documentation.
>>
>>
> The iosapic also using 32-bit to access registers:
>
> All registers are accessed using 32-bit uncacheable loads and stores to a reserved memory location
> in system memory. This implies that to modify a field (e.g., a bit or a byte) in any register, the
> whole 32-bit register must be read, the field modified, and the 32 bits written back. Partial register
> access, or non-aligned register access, are implementation-defined by the I/O xAPIC and will not
> be compatible across different implementations. Also, registers that are described as 64 bits wide
> are accessed as multiple independent 32-bit registers.
>
> [ From<< Intel® Itanium® Processor Family Interrupt Architecture Guide>>, P2-6 ]
>

Ok.

>> There might be guests that use incorrect access despite the
>> documentation; if real hardware supports it, it should work. So we need
>> to start with just a warning, and allow the access. Later we can drop
>> the invalid access.
>>
> If the OS contravene the spec, i thinks it's the OS's bug, also, i have tested some versions
> windows/linux guests, it's no broken, can we directly drop the other wide access?
>

Well, there's the spec and there's real life, but in this case we can
try and if we see a problem we'll re-add the other access length.

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