From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [PATCH v2] KVM: IOAPIC: only access APIC registers one dword at a time Date: Mon, 05 Jul 2010 10:54:20 +0300 Message-ID: <4C318FAC.8010605@redhat.com> References: <4C2D6D4B.5060309@cn.fujitsu.com> <4C2D95EA.6080209@np.css.fujitsu.com> <4C2D975A.2050704@cn.fujitsu.com> <4C2D9C8C.8060401@cn.fujitsu.com> <4C2F0CC1.6020808@redhat.com> <4C3155BA.4070903@cn.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Marcelo Tosatti , LKML , KVM list , Jin Dongming To: Xiao Guangrong Return-path: In-Reply-To: <4C3155BA.4070903@cn.fujitsu.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 07/05/2010 06:47 AM, Xiao Guangrong wrote: > > Avi Kivity wrote: > =20 >> On 07/02/2010 11:00 AM, Xiao Guangrong wrote: >> =20 >>> The IOAPIC spec says: >>> >>> When accessing these registers, accesses must be done one dword at = a >>> time. >>> For example, software should never access byte 2 from the Data >>> register before >>> accessing bytes 0 and 1. The hardware will not attempt to recover f= rom >>> a bad >>> programming model in this case. >>> >>> So, this patch removes other width access >>> >>> >>> =20 >> The ioapic code also implements the ia64 iosapic. I'm guessing that >> does support 64-bit accesses. Please check the iosapic documentatio= n. >> >> =20 > The iosapic also using 32-bit to access registers: > > All registers are accessed using 32-bit uncacheable loads and stores = to a reserved memory location > in system memory. This implies that to modify a field (e.g., a bit or= a byte) in any register, the > whole 32-bit register must be read, the field modified, and the 32 bi= ts written back. Partial register > access, or non-aligned register access, are implementation-defined by= the I/O xAPIC and will not > be compatible across different implementations. Also, registers that = are described as 64 bits wide > are accessed as multiple independent 32-bit registers. > > [ From<< Intel=C2=AE Itanium=C2=AE Processor Family Interrupt Archit= ecture Guide>>, P2-6 ] > =20 Ok. >> There might be guests that use incorrect access despite the >> documentation; if real hardware supports it, it should work. So we = need >> to start with just a warning, and allow the access. Later we can dr= op >> the invalid access. >> =20 > If the OS contravene the spec, i thinks it's the OS's bug, also, i ha= ve tested some versions > windows/linux guests, it's no broken, can we directly drop the other = wide access? > =20 Well, there's the spec and there's real life, but in this case we can=20 try and if we see a problem we'll re-add the other access length. --=20 error compiling committee.c: too many arguments to function