From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [Qemu-devel] Re: [RFC PATCH 4/7] ide: IOMMU support Date: Thu, 15 Jul 2010 20:02:05 +0300 Message-ID: <4C3F3F0D.1000103@redhat.com> References: <1279086307-9596-1-git-send-email-eduard.munteanu@linux360.ro> <4C3E2C2E.70507@codemonkey.ws> <20100714222401.GB21126@sequoia.sous-sol.org> <201007151128.27487.paul@codesourcery.com> <20100715165214.GV14017@sequoia.sous-sol.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Paul Brook , Anthony Liguori , Joerg Roedel , Eduard - Gabriel Munteanu , qemu-devel@nongnu.org, kvm@vger.kernel.org To: Chris Wright Return-path: Received: from mx1.redhat.com ([209.132.183.28]:28568 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933753Ab0GORCq (ORCPT ); Thu, 15 Jul 2010 13:02:46 -0400 In-Reply-To: <20100715165214.GV14017@sequoia.sous-sol.org> Sender: kvm-owner@vger.kernel.org List-ID: On 07/15/2010 07:52 PM, Chris Wright wrote: > >> Really? Can you provide an documentation to support this claim? >> My impression is that there is no difference between translated and >> untranslated devices, and the translation is explicitly disabled by software. >> > ATS allows an I/O device to request a translation from the IOMMU. > The device can then cache that translation and use the translated address > in a PCIe memory transaction. PCIe uses a couple of previously reserved > bits in the transaction layer packet header to describe the address > type for memory transactions. The default (00) maps to legacy PCIe and > describes the memory address as untranslated. This is the normal mode, > and could then incur a translation if an IOMMU is present and programmed > w/ page tables, etc. as is passes through the host bridge. > > Another type is simply a transaction requesting a translation. This is > new, and allows a device to request (and cache) a translation from the > IOMMU for subsequent use. > > The third type is a memory transaction tagged as already translated. > This is the type of transaction an ATS capable I/O device will generate > when it was able to translate the memory address from its own cache. > > Of course, there's also an invalidation request that the IOMMU can send > to ATS capable I/O devices to invalidate the cached translation. > For emulated device, it seems like we can ignore ATS completely, no? -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.